公开(公告)号：US20230209810A1

公开(公告)日：2023-06-29

申请号：US18046088

申请日：2022-10-12

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  David Ross Economy ,  John D. Hopkins ,  Jordan D. Greenlee ,  Mithun Kumar Ramasahayam

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10885 ,  H01L21/7682 ,  H01L27/1087 ,  H01L21/76837

Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes an electrically insulating material and bit lines including copper in the electrically insulating material. The electrically insulating material defines air gaps between the bit lines. A method of manufacturing a memory device includes forming trenches in an electrically insulating material on or in circuitry of the memory device, forming a first electrically conductive material in the trenches, removing portions of the electrically insulating material to form air gaps between the trenches, recessing the first electrically conductive material, and replacing the first electrically conductive material that was removed with a second electrically conductive material. The second electrically conductive material is more electrically conductive than the first electrically conductive material. A memory device includes the apparatus. A computing system includes the memory device.

公开(公告)号：US20240355363A1

公开(公告)日：2024-10-24

申请号：US18630919

申请日：2024-04-09

Applicant: Micron Technology, Inc.

Inventor： Mithun Kumar Ramasahayam ,  Indra V. Chary ,  Meng-Wei Kuo

IPC: G11C5/06 ,  G11C16/04 ,  H01L29/49 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C5/063 ,  G11C16/0483 ,  H01L29/4966 ,  H10B43/27 ,  H10B43/35

Abstract: Methods, systems, and devices for a bit line contact scheme in a memory system stack are described. A memory architecture may include bit lines coupled with bit line contacts, and pillars coupled with circuitry associated with supporting operation of the bit lines. Hybrid plugs may be integrated into the pillars to couple the bit line contacts with the pillars, forming a conductive path between the bit lines and the circuitry. The hybrid plugs may be recessed within the pillars such that the hybrid plugs do not extend through the memory architecture beyond the pillars. The hybrid plugs may include one or more relatively low capacitance, conductive materials, such as a titanium alloy material (e.g., titanium, titanium nitride), a tungsten alloy material (e.g., tungsten, tungsten nitride), or any combination thereof, among other materials.

公开(公告)号：US20230207458A1

公开(公告)日：2023-06-29

申请号：US18046111

申请日：2022-10-12

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  David Ross Economy ,  Jay S. Brown ,  John D. Hopkins ,  Jordan D. Greenlee ,  Mithun Kumar Ramasahayam ,  Rita J. Klein

IPC: H01L23/528 ,  H01L23/532 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/11556 ,  H01L27/11582

Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes bit lines including copper, a low-k dielectric material between the bit lines, and air gaps between the bit lines. The low-k dielectric material mechanically supports the bit lines. A method of manufacturing a memory device includes forming a first electrically conductive material in bit line trenches of an electrically insulating material, removing portions of the electrically insulating material between the bit line trenches, conformally forming a low-k dielectric material on the first electrically conductive material and remaining portions of the electrically insulating material, and forming a subconformal dielectric material to form air gaps between the bit line trenches. The method also includes recessing the first electrically conductive material and replacing removed portions of the first electrically conductive material with a second electrically conductive material.

公开(公告)号：US20230081678A1

公开(公告)日：2023-03-16

申请号：US18053626

申请日：2022-11-08

Applicant: Micron Technology, Inc.

Inventor： Mithun Kumar Ramasahayam ,  Michael J. Gossman

IPC: G11C7/18 ,  H01L29/06 ,  H01L27/11551

Abstract: An electronic device that comprises bitlines and air gaps adjacent to an array region of an electronic device is disclosed. The bitlines comprise sloped sidewalls and a height of the air gaps is greater than a height of the bitlines. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US20220157354A1

公开(公告)日：2022-05-19

申请号：US17097494

申请日：2020-11-13

Applicant: Micron Technology, Inc.

Inventor： Mithun Kumar Ramasahayam ,  Michael J. Gossman

IPC: G11C7/18 ,  H01L27/11551 ,  H01L29/06

Abstract: An electronic device that comprises bitlines and air gaps adjacent to an array region of an electronic device is disclosed. The bitlines comprise sloped sidewalls and a height of the air gaps is greater than a height of the bitlines. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.