公开(公告)号：US20230209818A1

公开(公告)日：2023-06-29

申请号：US17674478

申请日：2022-02-17

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Jordan D. Greenlee ,  Mithun Kumar Ramasahayam ,  Nancy M. Lomeli

IPC: H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/04

CPC classification number: H01L27/11519 ,  G11C16/0483 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/1157

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are between immediately-laterally-adjacent of the memory blocks. Conductor material is in and extends elevationally along sidewalls of the trenches laterally-over the conductive tiers and the insulative tiers and directly electrically couples together conducting material of individual of the conductive tiers. The conductor material is exposed to oxidizing conditions to form an insulative oxide laterally-through the conductor material laterally-over individual of the insulative tiers to separate the conducting material of the individual conductive tiers from being directly electrically coupled together by the conductor material. Additional embodiments are disclosed.

公开(公告)号：US11508421B2

公开(公告)日：2022-11-22

申请号：US17097494

申请日：2020-11-13

Applicant: Micron Technology, Inc.

Inventor： Mithun Kumar Ramasahayam ,  Michael J. Gossman

IPC: G11C7/18 ,  H01L29/06 ,  H01L27/11551 ,  H01L27/11524

Abstract: An electronic device that comprises bitlines and air gaps adjacent to an array region of an electronic device is disclosed. The bitlines comprise sloped sidewalls and a height of the air gaps is greater than a height of the bitlines. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US12243620B2

公开(公告)日：2025-03-04

申请号：US18053626

申请日：2022-11-08

Applicant: Micron Technology, Inc.

Inventor： Mithun Kumar Ramasahayam ,  Michael J. Gossman

IPC: G11C7/18 ,  H01L29/06 ,  H10B41/20 ,  H10B41/35

Abstract: An electronic device that comprises bitlines and air gaps adjacent to an array region of an electronic device is disclosed. The bitlines comprise sloped sidewalls and a height of the air gaps is greater than a height of the bitlines. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US11895834B2

公开(公告)日：2024-02-06

申请号：US17674478

申请日：2022-02-17

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Jordan D. Greenlee ,  Mithun Kumar Ramasahayam ,  Nancy M. Lomeli

IPC: H10B41/10 ,  G11C16/04 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B41/10 ,  G11C16/0483 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are between immediately-laterally-adjacent of the memory blocks. Conductor material is in and extends elevationally along sidewalls of the trenches laterally-over the conductive tiers and the insulative tiers and directly electrically couples together conducting material of individual of the conductive tiers. The conductor material is exposed to oxidizing conditions to form an insulative oxide laterally-through the conductor material laterally-over individual of the insulative tiers to separate the conducting material of the individual conductive tiers from being directly electrically coupled together by the conductor material. Additional embodiments are disclosed.

公开(公告)号：US20230395510A1

公开(公告)日：2023-12-07

申请号：US17812141

申请日：2022-07-12

Applicant: Micron Technology, Inc.

Inventor： Mithun Kumar Ramasahayam ,  Jordan D. Greenlee ,  Harsh Narendrakumar Jain ,  Jiewei Chen ,  Indra V. Chary

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53242 ,  H01L23/53257 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76888

Abstract: Microelectronic devices include a stack with a vertically alternating sequence of insulative and conductive structures arranged in tiers. A staircased stadium within the stack comprises steps at different tier elevations of a group of the tiers. Treads of the steps are each provided by an upper surface area of one of the conductive structures within the group of the tiers and by an upper surface area of a metal oxide region extending through the one of the conductive structures. A pair of conductive contact structures extends to one of the steps. A first conductive contact structure of the pair terminates at the tread of the step, within the area of the conductive structure. A second conductive contact structure of the pair extends through the tread of the step, within the upper surface area of the metal oxide region. Related fabrication methods and electronic systems are also disclosed.

公开(公告)号：US12272421B2

公开(公告)日：2025-04-08

申请号：US17895959

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Mithun Kumar Ramasahayam ,  Tomoko Ogura Iwasaki

IPC: G11C7/10

Abstract: A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars and forms a logic layer disposed above the memory array, the logic layer comprising a plurality of latches arranged along a plurality of logic layer latch pillars, the plurality of latches to store a multi-bit data pattern representing a sequence of bits to be programmed to the plurality of memory cells of the memory array.

公开(公告)号：US20240071505A1

公开(公告)日：2024-02-29

申请号：US18237815

申请日：2023-08-24

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Mithun Kumar Ramasahayam ,  Tomoko Ogura Iwasaki ,  June Lee ,  Luyen Vu

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3459

Abstract: Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.

公开(公告)号：US20230335193A1

公开(公告)日：2023-10-19

申请号：US17659102

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Mithun Kumar Ramasahayam

IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528

CPC classification number: G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/5283

Abstract: A microelectronic device comprises a stack structure comprising blocks each including a vertically alternating sequence of conductive material and insulative material arranged in tiers, at least one of the blocks comprising: a memory array region having vertically extending strings of memory cells within a horizontal area thereof; and a staircase region horizontally neighboring the memory array region. The staircase structure has steps comprising horizontal ends of the tiers; and a crest sub-region horizontally interposed between the staircase structure and the memory array region. A masking structure overlies the stack structure and has a different material composition than each of the conductive material and the insulative material. Filled slot structures are interposed between the blocks of the stack structure, at least one of the filled slot structures comprises at least one fill material that has an uppermost boundary vertically underlying an uppermost boundary of the masking structure.

公开(公告)号：US20250167055A1

公开(公告)日：2025-05-22

申请号：US18952448

申请日：2024-11-19

Applicant: Micron Technology, Inc.

Inventor： Mithun Kumar Ramasahayam ,  Amitava Majumdar ,  Jeffrey D. Runia ,  Merri L. Carlson

IPC: H01L21/66

Abstract: Semiconductor devices and associated methods are shown. A device may include an array of memory cells formed on a semiconductor substrate. A device may include one or more test pattern regions located at edges adjacent to the array of memory cells, the one or more test pattern regions including, an array of parallel conductive lines; and wherein selected lines of the array of parallel conductive lines are electrically coupled to ground to detect defects during a test procedure.

公开(公告)号：US20240071430A1

公开(公告)日：2024-02-29

申请号：US17895959

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Mithun Kumar Ramasahayam ,  Tomoko Ogura Iwasaki

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/064 ,  G06F3/0679

Abstract: A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars and forms a logic layer disposed above the memory array, the logic layer comprising a plurality of latches arranged along a plurality of logic layer latch pillars, the plurality of latches to store a multi-bit data pattern representing a sequence of bits to be programmed to the plurality of memory cells of the memory array.