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    STRESS MITIGATION FOR THREE-DIMENSIONAL METAL CONTACTS
    12.
    发明公开
    STRESS MITIGATION FOR THREE-DIMENSIONAL METAL CONTACTS 审中-公开

    公开(公告)号：US20240071819A1

    公开(公告)日：2024-02-29

    申请号：US18234111

    申请日：2023-08-15

    Applicant: Micron Technology, Inc.

    Inventor： Chandra S. Tiwari ,  Jivaan Kishore Jhothiraman ,  Rutuparna Narulkar ,  Nayan Chakravarty ,  Pengyuan Zheng ,  Hiroaki Iuchi

    IPC: H01L21/768 ,  H01L23/522

    CPC classification number: H01L21/76831 ,  H01L23/5226 ,  H10B43/27

    Abstract: A variety of applications can include apparatus having a memory device structured with a three-dimensional array of memory cells and one or more vertical metal contacts extending through levels of the memory device, where the one or more vertical metal contacts are formed with reduced stress. Each of the one or more vertical metal contacts can be constructed by forming a liner on walls of an opening in a dielectric, where the opening extends through the levels for the memory device, and forming a metal composition adjacent the liner and filling the opening with the metal composition. The liner can be removed from at least a portion of the walls of the dielectric, where the liner has a composition correlated to the metal composition such that removal of the liner reduces stress on the metal composition.

    Memory Circuitry And Method Used In Forming Memory Circuitry
    13.
    发明公开
    Memory Circuitry And Method Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240047346A1

    公开(公告)日：2024-02-08

    申请号：US17880444

    申请日：2022-08-03

    Applicant: Micron Technology, Inc.

    Inventor： Rutuparna Narulkar ,  Chandra Tiwari ,  Dmitry Mikulik ,  Erica A. Ellingson ,  Yucheng Wang ,  Mathew Thomas

    IPC: H01L23/522 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

    CPC classification number: H01L23/5228 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

    Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs. A lining has a specific resistance of at least 1×104 ohm·m at 20° C. atop treads of the stairs of the flight of stairs. Individual of the treads comprise conducting material of one of the conductive tiers. The lining comprises at least one of (a), (b), (c), and (d), where: (a): M1xM2yOz having a specific resistance of at least 1×104 ohm·m at 20° C. and where M1 and M2 are each a different one of Hf, Zr, Al, Ta, Sc, and Y; “z” is greater than zero; and at least one of “x” and “y” is greater than zero; (b) BtCwOv having a specific resistance of at least 1×104 ohm·m at 20° C. and where each of “t” and “v” is greater than zero (c): BrCs having a specific resistance of at least 1×104 ohm·m at 20° C. and where each of “r” and “s” is greater than zero; and (d): BkChNp having a specific resistance of at least 1×104 ohm·m at 20° C. and where each of “k” and “p” is greater than zero. Insulative material in the cavity is directly above the lining that comprises the at least one of the (a), the (b), the (c), and the (d). Conductive vias extend through the insulative material and the lining that comprises the at least one of the (a), the (b), the (c), and the (d). Individual of the conductive vias are directly above and directly against the conducting material of one of the individual treads. Methods are disclosed.

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