公开(公告)号：US20230018127A1

公开(公告)日：2023-01-19

申请号：US17379338

申请日：2021-07-19

Applicant: Micron Technology, Inc.

Inventor： Ramanathan Gandhi ,  Sock Mui Poh ,  Dmitry Mikulik ,  Dae Hong Eom ,  Moonhyeong Han ,  Aireus O. Christensen ,  Chandrasekaran Venkatasubramanian

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L25/065

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one pillar extends through the stack structure. The at least one pillar includes at least one insulative material and a channel structure horizontally surrounding the at least one insulative material. The at least one channel structure comprises sub-regions of semiconductor material. At least one of the sub-regions exhibits a different microstructure than at least one other of the sub-regions. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.

公开(公告)号：US20240194264A1

公开(公告)日：2024-06-13

申请号：US18515906

申请日：2023-11-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dmitry Mikulik ,  Leo Lukose ,  Ramanathan Gandhi

IPC: G11C16/04 ,  G11C5/06 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  G11C5/063 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: Memory cells, and memories and memory array structures containing such memory cells, might include a control gate, a channel, a gate dielectric between the channel and the control gate, a charge-storage node between the gate dielectric and the control gate, a charge-blocking material between the charge-storage node and the control gate, a laminated dielectric between the charge-blocking material and the control gate, and a high-K dielectric between the laminated dielectric and the control gate, wherein the laminated dielectric comprises an instance of a first dielectric material between the charge-blocking material and the high-K dielectric and an instance of a second dielectric material between the instance of the first dielectric material and the high-K dielectric, and wherein the instance of the first dielectric material has a higher oxygen areal density than an oxygen areal density of the instance of the second dielectric material.

公开(公告)号：US20240047346A1

公开(公告)日：2024-02-08

申请号：US17880444

申请日：2022-08-03

Applicant: Micron Technology, Inc.

Inventor： Rutuparna Narulkar ,  Chandra Tiwari ,  Dmitry Mikulik ,  Erica A. Ellingson ,  Yucheng Wang ,  Mathew Thomas

IPC: H01L23/522 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5228 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs. A lining has a specific resistance of at least 1×104 ohm·m at 20° C. atop treads of the stairs of the flight of stairs. Individual of the treads comprise conducting material of one of the conductive tiers. The lining comprises at least one of (a), (b), (c), and (d), where: (a): M1xM2yOz having a specific resistance of at least 1×104 ohm·m at 20° C. and where M1 and M2 are each a different one of Hf, Zr, Al, Ta, Sc, and Y; “z” is greater than zero; and at least one of “x” and “y” is greater than zero; (b) BtCwOv having a specific resistance of at least 1×104 ohm·m at 20° C. and where each of “t” and “v” is greater than zero (c): BrCs having a specific resistance of at least 1×104 ohm·m at 20° C. and where each of “r” and “s” is greater than zero; and (d): BkChNp having a specific resistance of at least 1×104 ohm·m at 20° C. and where each of “k” and “p” is greater than zero. Insulative material in the cavity is directly above the lining that comprises the at least one of the (a), the (b), the (c), and the (d). Conductive vias extend through the insulative material and the lining that comprises the at least one of the (a), the (b), the (c), and the (d). Individual of the conductive vias are directly above and directly against the conducting material of one of the individual treads. Methods are disclosed.