公开(公告)号：US11429479B2

公开(公告)日：2022-08-30

申请号：US16931178

申请日：2020-07-16

Applicant: Micron Technology, Inc.

Inventor： Sai Krishna Mylavarapu

IPC: G06F11/10 ,  G06F11/07 ,  G06F12/02 ,  G06F11/30

Abstract: Various embodiments described herein provide for copying (e.g., to cache) a portion of defect management data for a block of a memory device, such as a non-volatile memory device of a memory sub-system, based on activity of the memory device. For instance, the portion of defect management data can be copied from a first-type memory device of the memory sub-system to a second-type memory device of the memory sub-system, where the first-type memory device stores defect management data for a working set of blocks of the non-volatile memory device being operated upon by the memory sub-system, where the second-type memory device is used to store defect management data for an active block of the working set of blocks, and where the second-type memory device has a faster access (e.g., read or write access) than the first-type memory device.

公开(公告)号：US20220197737A1

公开(公告)日：2022-06-23

申请号：US17130885

申请日：2020-12-22

Applicant: Micron Technology, Inc.

Inventor： Sai Krishna Mylavarapu ,  Todd A. Marquart

IPC: G06F11/10 ,  G11C11/00

Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

公开(公告)号：US20210304826A1

公开(公告)日：2021-09-30

申请号：US17347570

申请日：2021-06-14

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Sai Krishna Mylavarapu ,  Zhenlei Shen ,  Tingjun Xie ,  Charles S. Kwong

IPC: G11C16/34 ,  G11C29/52 ,  G06F11/10 ,  G11C16/26 ,  G11C29/42 ,  G06F11/07 ,  G06F11/14 ,  G11C29/44

Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device determines that a bit error rate (BER) corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion, determines a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component, and determines whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data. The processing device initiates a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.

公开(公告)号：US20200185045A1

公开(公告)日：2020-06-11

申请号：US16215267

申请日：2018-12-10

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Sai Krishna Mylavarapu ,  Zhenlei Shen ,  Tingjun Xie ,  Charles S. Kwong

IPC: G11C16/34 ,  G11C29/52 ,  G06F11/10 ,  G11C16/26 ,  G11C29/44 ,  G11C29/42 ,  G06F11/07 ,  G06F11/14

Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device performs an error recovery flow (ERF) to recover a unit of data comprising data and a write timestamp indicating when the unit of data was written. The processing device determines whether to perform a defect detection operation to detect a defect in the memory component using a bit error rate (BER), corresponding to the read operation, and the write timestamp in the unit of data. The processing device initiates the defect detection operation responsive to the BER condition not being expected for the calculated W2R (based on the write timestamp). The processing device can use an ERF condition and the write timestamp to determine whether to perform the defect detection operation. The processing device initiates the defect detection operation responsive to the ERF condition not being expected the calculated W2R (based on the write timestamp).

公开(公告)号：US20240404581A1

公开(公告)日：2024-12-05

申请号：US18667791

申请日：2024-05-17

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Brent Keeth ,  James Brian Johnson ,  Chun-Yi Liu ,  Shivasankar Gunasekaran ,  Paul A. Laberge ,  Gregory A. King ,  Sai Krishna Mylavarapu ,  Su Wei Lim ,  Nathan A. Eckel ,  Lance P. Johnson ,  Nathan D. Henningson

IPC: G11C11/4093 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: Methods, systems, and devices for interface techniques for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute memory access circuitry among multiple semiconductor dies of a stack. A first die of the system may include logic circuitry operable to configure a set of multiple first interface blocks of the first die. Each first interface block may include circuitry operable to communicate with one or more second interface blocks of one or more second dies of the system to access a respective set of one or more memory arrays of the one or more second dies. In some examples, the system may include a respective controller for each first interface block to support access operations via the first interface block. The system may also include non-volatile storage, one or more sensors, or a combination thereof to support various operations of the system.

公开(公告)号：US11768633B2

公开(公告)日：2023-09-26

申请号：US17965510

申请日：2022-10-13

Applicant: Micron Technology, Inc.

Inventor： Sai Krishna Mylavarapu

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0652 ,  G06F3/0679 ,  G06F2212/7209

Abstract: Various embodiments described herein provide for performing inversion refresh of a physical memory location of a memory device (e.g., memory cell on a negative-and (NAND)-type memory device) based on a state of the physical memory location. For some embodiments, the inversion refresh is performed as part of performing garbage collection or reclamation of physical memory locations of a memory device.

公开(公告)号：US20230029959A1

公开(公告)日：2023-02-02

申请号：US17965510

申请日：2022-10-13

Applicant: Micron Technology, Inc.

Inventor： Sai Krishna Mylavarapu

IPC: G06F3/06

Abstract: Various embodiments described herein provide for performing inversion refresh of a physical memory location of a memory device (e.g., memory cell on a negative-and (NAND)-type memory device) based on a state of the physical memory location. For some embodiments, the inversion refresh is performed as part of performing garbage collection or reclamation of physical memory locations of a memory device.

公开(公告)号：US11494124B2

公开(公告)日：2022-11-08

申请号：US17177802

申请日：2021-02-17

Applicant: Micron Technology, Inc.

Inventor： Sai Krishna Mylavarapu

IPC: G06F3/06

Abstract: Various embodiments described herein provide for performing inversion refresh of a physical memory location of a memory device (e.g., memory cell on a negative-and (NAND)-type memory device) based on a state of the physical memory location. For some embodiments, the inversion refresh is performed as part of performing garbage collection or reclamation of physical memory locations of a memory device.

公开(公告)号：US20220019502A1

公开(公告)日：2022-01-20

申请号：US16931178

申请日：2020-07-16

Applicant: Micron Technology, Inc.

Inventor： Sai Krishna Mylavarapu

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02

Abstract: Various embodiments described herein provide for copying (e.g., to cache) a portion of defect management data for a block of a memory device, such as a non-volatile memory device of a memory sub-system, based on activity of the memory device. For instance, the portion of defect management data can be copied from a first-type memory device of the memory sub-system to a second-type memory device of the memory sub-system, where the first-type memory device stores defect management data for a working set of blocks of the non-volatile memory device being operated upon by the memory sub-system, where the second-type memory device is used to store defect management data for an active block of the working set of blocks, and where the second-type memory device has a faster access (e.g., read or write access) than the first-type memory device.

公开(公告)号：US10431286B2

公开(公告)日：2019-10-01

申请号：US16218787

申请日：2018-12-13

Applicant: Micron Technology, Inc.

Inventor： Sai Krishna Mylavarapu

IPC: G11C7/00 ,  G11C11/401 ,  G11C16/34 ,  G06F12/02

Abstract: The present disclosure includes apparatuses and methods related to refresh in memory. An example apparatus can refresh a memory cell of an array of memory cells in response to the array of memory cells being accessed a threshold number of accesses.