公开(公告)号：US20220391321A1

公开(公告)日：2022-12-08

申请号：US17547818

申请日：2021-12-10

Applicant: Micron Technology, Inc.

Inventor： Sundararajan Sankaranarayanan ,  Eric N. Lee

IPC: G06F12/084 ,  G06F3/06 ,  G06F12/0882 ,  G11C16/24 ,  G11C16/26

Abstract: A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.

公开(公告)号：US20250028466A1

公开(公告)日：2025-01-23

申请号：US18774244

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： Aswin Thiruvengadam ,  Sundararajan Sankaranarayanan ,  Ahmet Kaya ,  Josh Hieb ,  Jay Sarkar

IPC: G06F3/06

Abstract: A processing device, operatively coupled with a memory device, determines a current workload characteristic of the memory device. The processing device further determines, by a trainable classifier processing the current workload characteristic, a first set of one or more parameter values that satisfies a threshold workload criterion associated with the memory device. The processing device further configures the firmware component of the memory device with the first set of one or more parameter values.

公开(公告)号：US20240311307A1

公开(公告)日：2024-09-19

申请号：US18671846

申请日：2024-05-22

Applicant: Micron Technology, Inc.

Inventor： Sundararajan Sankaranarayanan ,  Eric N. Lee

IPC: G06F12/084 ,  G06F3/06 ,  G06F12/0882 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

CPC classification number: G06F12/084 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0882 ,  G11C16/24 ,  G11C16/26 ,  G06F2212/1024 ,  G06F2212/222 ,  G11C16/0483

Abstract: A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.

公开(公告)号：US12019550B2

公开(公告)日：2024-06-25

申请号：US17547818

申请日：2021-12-10

Applicant: Micron Technology, Inc.

Inventor： Sundararajan Sankaranarayanan ,  Eric N. Lee

IPC: G06F12/084 ,  G06F3/06 ,  G06F12/0882 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

CPC classification number: G06F12/084 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0882 ,  G11C16/24 ,  G11C16/26 ,  G06F2212/1024 ,  G06F2212/222 ,  G11C16/0483

Abstract: A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.

公开(公告)号：US11947452B2

公开(公告)日：2024-04-02

申请号：US17830047

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Xiangyu Tang ,  David Ebsen ,  Ying Huang ,  Sundararajan Sankaranarayanan

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0253 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0679

Abstract: A subset of blocks from a set of blocks of a memory device are identified based on a valid data count constraint. A first block from the subset of blocks is selected based on a valid data count of the first block. A second block from the subset of blocks is selected based on a data temperature of the second block. A comparison of the first block and the second block is performed in accordance with one or more comparison criterion. The first block or the second block is selected as a garbage collection source block based on the comparison. Garbage collection is performed at the garbage collection source block.

公开(公告)号：US11861233B2

公开(公告)日：2024-01-02

申请号：US17691467

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Kishore Kumar Muchherla ,  Sivagnanam Parthasarathy ,  Patrick R. Khayat ,  Sundararajan Sankaranarayanan ,  Jeremy Binfet ,  Akira Goda

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/04

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673 ,  G11C16/26 ,  G11C16/0483

Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving data to be stored on the memory device, storing a first copy of the data in a first set of memory cells of the memory device, and storing a second copy of the data in a second set of memory cells of the memory device. The operations can also include reading the first copy of the data and determining whether a threshold voltage of a cell in the first set of memory cells is within an overlapping range of voltage distributions, and reading the second copy of the data and determining whether the threshold voltage of a cell in the second set of memory cells is within an overlapping range of voltage distributions. They can also include using the second copy of the data.

公开(公告)号：US20230214139A1

公开(公告)日：2023-07-06

申请号：US17858778

申请日：2022-07-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sundararajan Sankaranarayanan ,  Eric N. Lee

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0656 ,  G06F3/0679

Abstract: A second read command to read second data from an array of memory cells is detected. An initial voltage to be applied to at least one wordline coupled to at least a subset of the array of memory cells is caused prior to releasing a first data associated with a first read command stored in a page buffer. The initial voltage to increase to a target value is caused. The page buffer to sense the second data from a bitline coupled to a page of the subset of the array of memory cells is caused. The sensed second data out of the bitline into the page buffer is read responsive to determining that the first data has been released from the page buffer.

公开(公告)号：US20230195385A1

公开(公告)日：2023-06-22

申请号：US17691467

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Kishore Kumar Muchherla ,  Sivagnanam Parthasarathy ,  Patrick Khayat ,  Sundararajan Sankaranarayanan ,  Jeremy Binfet ,  Akira Goda

IPC: G06F3/06 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G11C16/26 ,  G06F3/0619 ,  G06F3/0673 ,  G11C16/0483

Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving data to be stored on the memory device, storing a first copy of the data in a first set of memory cells of the memory device, and storing a second copy of the data in a second set of memory cells of the memory device. The operations can also include reading the first copy of the data and determining whether a threshold voltage of a cell in the first set of memory cells is within an overlapping range of voltage distributions, and reading the second copy of the data and determining whether the threshold voltage of a cell in the second set of memory cells is within an overlapping range of voltage distributions. They can also include using the second copy of the data.

公开(公告)号：US11568921B2

公开(公告)日：2023-01-31

申请号：US17318579

申请日：2021-05-12

Applicant: Micron Technology, Inc.

Inventor： Koichi Kawai ,  Sundararajan Sankaranarayanan ,  Eric Nien-Heng Lee ,  Akira Goda

IPC: G11C7/00 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4093 ,  G11C11/4074 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04

Abstract: A device includes an array of memory cells having a word line coupled to at least a subset of the array, a queue, and control logic. The control logic: detects a first read command to read first data from a first page of the subset; accesses a second read command in the queue, the second read command to read second data from a second page of the subset; causes a voltage applied to the word line to ramp up to an initial value; causes the voltage to move to a target value; directs a page buffer to sense the first data from a first bit line coupled to the first page of the subset; directs the page buffer to sense the second data from a second bit line coupled to the second page of the subset; and causes the word line to be discharged.

公开(公告)号：US20250110669A1

公开(公告)日：2025-04-03

申请号：US18788786

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Sundararajan Sankaranarayanan ,  Sampath Ratnam ,  Jiangang Wu ,  Chandra Mouli Guda ,  Steven R. Brown ,  Ashutosh Malshe

IPC: G06F3/06

Abstract: The disclosure configures a memory sub-system controller to store random data in a different layout from sequential data. The controller receives a request to store a set of data to a set of memory components. The controller determines whether the set of data corresponds to either sequential data or random data and selects a write cursor from a plurality of write cursors to associate with the set of data in response to determining whether the set of data corresponds to the sequential data or the random data. The controller programs the set of data to one or more of the set of memory components according to a data layout associated with the selected write cursor.