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公开(公告)号：US11385949B2
公开(公告)日：2022-07-12
申请号：US17092778
申请日：2020-11-09
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Suresh Rajgopal , Dan E. Soto , Steven Eskildsen
Abstract: Apparatus having a plurality of sets of memory devices and a multiplexer, wherein each set of memory devices of the plurality of sets of memory devices corresponds to a respective enable signal of a plurality of enable signals, wherein, for each set of memory devices of the plurality of sets of memory devices, each memory device of that set of memory devices is configured to receive commands in response to the respective enable signal for that set of memory devices having a particular logic level, and wherein, for each set of memory devices of the plurality of sets of memory devices, the multiplexer is configured to selectively connect input/output signal lines of that set of memory devices to an interface of the apparatus in response to the respective enable signal for that set of memory devices.
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公开(公告)号：US20210034290A1
公开(公告)日：2021-02-04
申请号：US16526649
申请日：2019-07-30
Applicant: Micron Technology, Inc.
Inventor： Marc S. Hamilton , Suresh Rajgopal
IPC: G06F3/06
Abstract: One or more requests are received from a host system while a media management scan is in progress on a memory component in a memory sub-system. The media management scan in progress is suspended. The request received from the host system are serviced. Once the host system is serviced, the media management scan is resumed on the memory component.
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公开(公告)号：US20150270851A1
公开(公告)日：2015-09-24
申请号：US14218315
申请日：2014-03-18
Applicant: Micron Technology, Inc.
Inventor： Joe F. Holt , Suresh Rajgopal , Jacob B. Derouen , Benjamin G. Hess
CPC classification number: G06F11/1076 , H03M13/1105 , H03M13/6505
Abstract: Generally discussed herein are Low Density Parity Check (LDPC) circuit layouts. An example LDPC circuit can include combinational logic and a plurality of memory units. Each of the plurality of memory units can be electrically coupled to each other and the combinational logic, and the plurality of memory units can be situated in a ring-like configuration.
Abstract translation: 这里通常讨论的是低密度奇偶校验（LDPC）电路布局。 示例性LDPC电路可以包括组合逻辑和多个存储器单元。 多个存储器单元中的每一个可以彼此电耦合并且组合逻辑，并且多个存储器单元可以位于环状配置中。
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公开(公告)号：US20250045217A1
公开(公告)日：2025-02-06
申请号：US18924299
申请日：2024-10-23
Applicant: Micron Technology, Inc.
Inventor： Suresh Rajgopal , Chulbum Kim , Dustin J. Carter
Abstract: A reference clock signal is received by an active input/output expander (AIOE), from a memory sub-system controller, via a first interface of the AIEO. A signal corresponding to data associated with an input/output (I/O) command is received from a memory device, via a second interface of the AIOE. The signal corresponding to the data is converted to a first interface-compliant signal based on the reference clock signal. The first interface-compliant signal is sent to the memory sub-system controller via the first interface.
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公开(公告)号：US12130755B2
公开(公告)日：2024-10-29
申请号：US17468264
申请日：2021-09-07
Applicant: Micron Technology, Inc.
Inventor： Suresh Rajgopal , Chulbum Kim , Dustin J. Carter
CPC classification number: G06F13/1668 , G06F12/10 , G06F13/4234 , G06F13/4282 , G11C16/0483 , H03M9/00
Abstract: An input/output (I/O) command referencing a logical address of a memory sub-system is received by an active input/output expander (AIOE). The I/O command is received from a memory sub-system controller via the AIOE. The AIOE identifies a physical block address corresponding to the logical block address. The AIOE identifies, among a plurality of memory devices, a memory device associated with the physical block address. The AIOE converts the I/O command received via the serial interface to a parallel interface compliant I/O command. The AIOE sends the parallel interface compliant I/O command to the memory device.
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Patent Agency Ranking
公开(公告)号：US11675696B2
公开(公告)日：2023-06-13
申请号：US17474867
申请日：2021-09-14
Applicant: Micron Technology, Inc.
Inventor： Suresh Rajgopal , Jeremy W. Butterfield , Sean E. Nerich , Dustin J. Carter
IPC: G06F12/02 , G06F12/0831 , G06F9/54 , G06F12/0882 , G06F12/0868
CPC classification number: G06F12/0246 , G06F9/544 , G06F12/0835 , G06F12/0868 , G06F12/0882
Abstract: A value setting associated with one or more parameters of a host-side interface and a memory-side interface of an input/output (I/O) expander is configured to enable Open NAND Flash Interface (ONFI)-compliant communications between a host system and a target memory die of a memory sub-system. The I/O expander processes one or more ONFI-compliant communications between the host system and the target memory die, wherein the one or more ONFI-compliant communications relate to execution of a memory access operation.
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公开(公告)号：US11455107B2
公开(公告)日：2022-09-27
申请号：US16666351
申请日：2019-10-28
Applicant: Micron Technology, Inc.
Inventor： Suresh Rajgopal , Ling Wang , Yue Wei , Vamsi Pavan Rayaprolu
IPC: G06F3/06
Abstract: A method is implemented for a memory sub-system that detects a sequential write pattern in a write sequence for a memory device in a set of commands received from a host, detects current bandwidth utilization deviating from a write bandwidth utilization performance target, in response to detecting the sequential write pattern, and adjusts write bandwidth utilization to conform to the write bandwidth utilization target, in response to detecting the current bandwidth utilization deviating from the write bandwidth utilization performance target.
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公开(公告)号：US11237754B2
公开(公告)日：2022-02-01
申请号：US16709614
申请日：2019-12-10
Applicant: Micron Technology, Inc.
Inventor： Chandra M. Guda , Suresh Rajgopal
IPC: G06F3/06
Abstract: A processing device receives a request to perform an erase operation on a memory device. The processing device executes a portion of the erase operation during a first time period. The processing device further executes an erase suspend operation to suspend the erase operation during the first time period. Responsive to detecting a completion of the erase suspend operation, the processing device receives one or more commands directed to the memory device. The processing device also executes the one or more commands during a second time period. Responsive to the expiration of the second time period, the processing device executes an erase resume operation to resume the erase operation on the memory device.
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公开(公告)号：US20210173771A1
公开(公告)日：2021-06-10
申请号：US16709380
申请日：2019-12-10
Applicant: Micron Technology, Inc.
Inventor： Suresh Rajgopal , Jeremy W. Butterfield , Sean E. Nerich , Dustin J. Carter
IPC: G06F12/02 , G06F12/0831 , G06F12/0868 , G06F12/0882 , G06F9/54
Abstract: A read command to read a target memory die of a memory sub-system is received from a host system via a host-side interface of an active input/output (I/O) expander. The active I/O expander identifies a page address corresponding to the target memory die and decodes the read command to send to a memory stack associated with the page address corresponding to the target memory die. Read data is received via a memory-side interface of the active I/O expander from the memory stack including the target memory die. A signal conditioning operation is performed on the read data to generate conditioned read data. The active I/O expander sends, via the host-side interface, the conditioned read data to the host system.
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公开(公告)号：US09411684B2
公开(公告)日：2016-08-09
申请号：US14218315
申请日：2014-03-18
Applicant: Micron Technology, Inc.
Inventor： Joe F. Holt , Suresh Rajgopal , Jacob B. Derouen , Benjamin G. Hess
CPC classification number: G06F11/1076 , H03M13/1105 , H03M13/6505
Abstract: Generally discussed herein are Low Density Parity Check (LDPC) circuit layouts. An example LDPC circuit can include combinational logic and a plurality of memory units. Each of the plurality of memory units can be electrically coupled to each other and the combinational logic, and the plurality of memory units can be situated in a ring-like configuration.
Abstract translation: 这里通常讨论的是低密度奇偶校验（LDPC）电路布局。 示例性LDPC电路可以包括组合逻辑和多个存储器单元。 多个存储器单元中的每一个可以彼此电耦合并且组合逻辑，并且多个存储器单元可以位于环状配置中。
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