公开(公告)号：US20200073589A1

公开(公告)日：2020-03-05

申请号：US16119766

申请日：2018-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vijayakrishna J. Vankayala

IPC: G06F3/06 ,  G11C7/22 ,  H03K23/40 ,  G11C7/10

Abstract: Memory devices and methods utilize pipelines to process or control timing of commands received by the memory device. They may also use tracking circuitry configured to determine whether one or more of the commands are in the pipeline. The tracking circuitry includes an input counter configured to count commands entering into the pipeline and an output counter configured to count commands exiting the pipeline. Furthermore, the tracking circuitry includes comparison circuitry configured to compare values in the input counter and the output counter and to output a command-in-pipeline signal indicative of the one or more commands being in the pipeline when the values in the input counter and the output counter differ.

公开(公告)号：US11967373B2

公开(公告)日：2024-04-23

申请号：US17831311

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala ,  Hari Giduturi ,  Jeffrey E. Koelling ,  Mingdong Cui ,  Ramachandra Rao Jogu

IPC: G11C13/00 ,  H03K19/20

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  G11C2213/15 ,  H03K19/20

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.

公开(公告)号：US20230395565A1

公开(公告)日：2023-12-07

申请号：US17887362

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L24/49 ,  H01L2224/49107 ,  H01L2224/4911 ,  H01L2224/49174 ,  H01L2224/49421 ,  H01L2924/1434

Abstract: Systems, methods, and devices related to techniques for reducing inter-die signal loads within a multi-die package are disclosed. The multi-die package includes a first memory die handling interfacing with a host for the package and at least one second memory die coupled to and configured to communication with the first memory die via an inter-die connection. A technique involves adding an additional wirebond pad to each die in the multi-die package. When the inter-die connections are made, the wirebond pad associated with the first memory die transmitter is connected to the wirebond pad associated with the receiver of a second memory die that is not connected to the transmitter of the second memory die. By not connecting to the transmitter of the second memory die, the first memory die transmits inter-die signals to the second memory die such that a lower signal load is achieved within the multi-die package.

公开(公告)号：US20230395145A1

公开(公告)日：2023-12-07

申请号：US17831311

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala ,  Hari Giduturi ,  Jeffrey E. Koelling ,  Mingdong Cui ,  Ramachandra Rao Jogu

IPC: G11C13/00

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  H03K19/20

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.

公开(公告)号：US20230267974A1

公开(公告)日：2023-08-24

申请号：US17652233

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1012 ,  G11C7/1063 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/1066

Abstract: Methods, systems, and devices for read operations for a memory array and register are described. In some examples, a memory device may include one or more memory arrays and one or more registers (e.g., one or more mode registers). The memory device may include circuitry that allows for a command to access a memory array and a command to access a register to be received consecutively (e.g., during consecutive sets of clock cycles). Because the commands may be received during consecutive sets of clock cycles, the corresponding data may also be output from the memory array and register during consecutive clock cycles.

公开(公告)号：US11727979B2

公开(公告)日：2023-08-15

申请号：US17369055

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder ,  Navya Sri Sreeram ,  William C. Waldrop ,  Vijayakrishna J. Vankayala

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F3/06 ,  G11C7/10

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4096 ,  G11C2207/2254

Abstract: Methods of operating a memory device are disclosed. A method may include asserting, at a semiconductor device, an internal signal in response to receipt of a command. The method may also include holding the internal signal in an asserted state for at least a predetermined time duration upon assertion of the internal signal. Further, the method may include generating an enable signal based on the internal signal and a clock signal. Associated devices and systems are also disclosed.

公开(公告)号：US11164613B2

公开(公告)日：2021-11-02

申请号：US16700212

申请日：2019-12-02

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala

IPC: G11C11/408 ,  G11C7/22 ,  G11C7/10 ,  G11C7/06

Abstract: Methods of operating a memory device are disclosed. A method may include receiving, at a first die of a number of dies, a first number of bits including one or more command bits, one or more identification bits, and a first number of address bits associated with a command during a first clock cycle. The method may further include conveying, from the first die to at least one other die, at least some of the first number of bits. Further, the method may include receiving, at the first die, a second number of bits including a second number of address bits associated with the command during a second, subsequent clock cycle. Also, the method may include conveying, from the first die to the at least one other die, at least some of the second number of bits. Memory devices and electronic systems are also disclosed.

公开(公告)号：US11094363B2

公开(公告)日：2021-08-17

申请号：US16825759

申请日：2020-03-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vijayakrishna J. Vankayala

IPC: G06F12/00 ,  G11C11/406 ,  G06F1/10 ,  G06F3/06 ,  G11C11/409

Abstract: Devices and methods include organizing memory units of a memory device into a number of groups. The devices and methods also include self-refreshing each group of memory units on different corresponding sequential clock pulses of a self-refresh clock. Specifically, at least one of each group of memory units counts pulses of a self-refresh clock and invokes a self-refresh after every nth pulse of a cycle of pulses while not invoking a self-refresh on all other pulses of the cycle of pulses.

公开(公告)号：US20210249058A1

公开(公告)日：2021-08-12

申请号：US17240921

申请日：2021-04-26

Applicant: Micron Technology, Inc.

Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala ,  Todd A. Dauenbaugh

IPC: G11C7/22

Abstract: A memory device includes a first data driver configured to send according to a first clock signal a first data to a first data port; a second data driver configured to send according to a second clock signal a second data to a second data port, wherein the second clock signal does not match the first clock signal.

公开(公告)号：US10896703B2

公开(公告)日：2021-01-19

申请号：US16523952

申请日：2019-07-26

Applicant: Micron Technology, Inc.

Inventor： Scott E. Smith ,  Vijayakrishna J. Vankayala

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/408 ,  G11C11/4093

Abstract: A memory device includes: a set of input pads configured to receive from a source external to the memory device one or more input signals and a chip select signal; an operation circuit electrically coupled to the input pads, operation circuit configured to perform operations corresponding to the one or more input signals when the chip select signal is enabled; and an input management circuit electrically coupled to and between the input pads and the operation circuit, the input management circuit configured to control propagation of the one or more input signals based on the chip select signal.