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公开(公告)号：US20190108867A1
公开(公告)日：2019-04-11
申请号：US16189425
申请日：2018-11-13
Applicant: Micron Technology, Inc.
Inventor： Xinwei Guo , Daniele Vimercati
IPC: G11C11/22
CPC classification number: G11C11/2273 , G11C11/221 , G11C11/2275
Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.
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公开(公告)号：US10121526B2
公开(公告)日：2018-11-06
申请号：US15689940
申请日：2017-08-29
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati , Xinwei Guo
Abstract: Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. Such redundant memory cells may be used if a another memory cell is discovered to be defective in some way; for example, after the array is fabricated and before deployment, defects in portions of the array that affect certain memory cells may be identified. Memory cells may be designated as redundant cells for numerous other memory cells of the array so that a total number of redundant cells in the array is relatively small fraction of the total number of cells of the array. A configuration of switching components may allow redundant cells to be operated in a manner that supports redundancy for numerous other cells and may limit or disturbances to neighboring cells when accessing redundancy cells.
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公开(公告)号：US09620207B2
公开(公告)日：2017-04-11
申请号：US15004781
申请日：2016-01-22
Applicant: Micron Technology, Inc.
Inventor： Xinwei Guo , Mingdong Cui
CPC classification number: G11C13/004 , G05F1/461 , G05F3/16 , G11C5/147 , G11C7/062 , G11C7/14 , G11C8/08 , G11C13/0004 , G11C13/0038 , G11C2013/0054
Abstract: Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which may be a PCM memory cell. The sensing circuits may include a cascode transistor. Examples of reference voltage generators may include a global reference voltage generator coupled to multiple bank reference voltage generators which may reduce an output resistance of the voltage generator routing.
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公开(公告)号：US20160141028A1
公开(公告)日：2016-05-19
申请号：US15004781
申请日：2016-01-22
Applicant: Micron Technology, Inc.
Inventor： Xinwei Guo , Mingdong Cui
CPC classification number: G11C13/004 , G05F1/461 , G05F3/16 , G11C5/147 , G11C7/062 , G11C7/14 , G11C8/08 , G11C13/0004 , G11C13/0038 , G11C2013/0054
Abstract: Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which may be a PCM memory cell. The sensing circuits may include a cascode transistor. Examples of reference voltage generators may include a global reference voltage generator coupled to multiple bank reference voltage generators which may reduce an output resistance of the voltage generator routing.
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公开(公告)号：US20150029806A1
公开(公告)日：2015-01-29
申请号：US14241257
申请日：2013-04-18
Applicant: Micron Technology, Inc.
Inventor： Liang Qiao , Xinwei Guo
CPC classification number: G11C5/147 , H02M3/07 , H02M2001/0025
Abstract: Voltage control in integrated circuits include a first voltage divider coupled to receive a reference voltage and having an output providing an adjusted reference voltage; an operational amplifier having a first input coupled to receive the output of the first voltage divider, a second input coupled to receive a feedback voltage, and an output; a voltage generation circuit responsive to the output of the operational amplifier and having an output providing an output voltage; and a second voltage divider coupled to receive the output voltage and having an output providing the feedback voltage. The first voltage divider is responsive to first control signals to adjust a voltage level of the adjusted reference voltage. The second voltage divider is responsive to second control signals to adjust a voltage level of the feedback voltage.
Abstract translation: 集成电路中的电压控制包括耦合以接收参考电压并且具有提供调整的参考电压的输出的第一分压器; 运算放大器，其具有耦合以接收第一分压器的输出的第一输入，耦合以接收反馈电压的第二输入和输出; 电压产生电路，其响应于所述运算放大器的输出并具有提供输出电压的输出; 以及耦合以接收输出电压并具有提供反馈电压的输出的第二分压器。 第一分压器响应于第一控制信号来调节调整的参考电压的电压电平。 第二分压器响应于第二控制信号来调节反馈电压的电压电平。
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Patent Agency Ranking
公开(公告)号：US20140204688A1
公开(公告)日：2014-07-24
申请号：US14222861
申请日：2014-03-24
Applicant: Micron Technology, Inc.
Inventor： Mingdong Cui , Xinwei Guo
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C7/14
Abstract: Example reference current distribution circuitry described herein include current mirrors having resistive elements of varying sizes between gate nodes of sense amplifier transistors along a voltage, distribution line. Examples of counter coupling capacitances which may be coupled to the gate nodes of sense amplifier transistors are also described.
Abstract translation: 本文描述的示例性参考电流分配电路包括电流镜，其具有沿着电压，分布线的读出放大器晶体管的栅极节点之间具有不同尺寸的电阻元件 还描述了可耦合到读出放大器晶体管的栅极节点的计数耦合电容的示例。
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公开(公告)号：US12027192B2
公开(公告)日：2024-07-02
申请号：US17470655
申请日：2021-09-09
Applicant: Micron Technology, Inc.
Inventor： Xinwei Guo , Daniele Vimercati
IPC: G11C11/22
CPC classification number: G11C11/2273 , G11C11/221 , G11C11/2275
Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.
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18.发明申请公开(公告)号：US20210335408A1
公开(公告)日：2021-10-28
申请号：US17236741
申请日：2021-04-21
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati , Xinwei Guo
IPC: G11C11/22 , G11C11/4094 , G11C11/4091
Abstract: Methods, systems, and devices for differential amplifier schemes for non-switching state compensation are described. During a read operation, a first node of a memory cell may be coupled with an input of differential amplifier while a second node of the memory cell may be biased with a first voltage (e.g., to apply a first read voltage across the memory cell). The second node of the memory cell may subsequently be biased with a second voltage (e.g., to apply a second read voltage across the memory cell), which may support the differential amplifier operating in a manner that compensates for a non-switching state of the memory cell. By compensating for a non-switching state of a memory cell during read operations, read margins may be increased.
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公开(公告)号：US20200294573A1
公开(公告)日：2020-09-17
申请号：US16854239
申请日：2020-04-21
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati , Stefan Frederik Schippers , Xinwei Guo
IPC: G11C11/4091 , G11C11/408 , H03F3/45 , G11C11/22
Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.
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公开(公告)号：US20190325941A1
公开(公告)日：2019-10-24
申请号：US15957790
申请日：2018-04-19
Applicant: Micron Technology, Inc.
Inventor： Xinwei Guo , Daniele Vimercati
Abstract: Methods and apparatus for sensing a memory cell using lower offset, higher speed sense amplifiers are described. A sense amplifier may include an amplifier component that is configurable to operate in an amplifier mode or a latch mode. In some examples, the amplifier component may be configured to operate in the amplifier or latch mode by activating or deactivating switching components inside the amplifier component. When configured to operate in the amplifier mode, the amplifier component may be used, during a read operation of a memory cell, to pre-charge a digit line and/or amplify a signal received from the memory cell. When configured to operate in the latch mode, the amplifier component may be used to latch a state of the memory cell. In some cases, the amplifier component may use some of the same internal circuitry for pre-charging the digit line, amplifying the signal, and/or latching the state.
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