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    Method of shaping sheet glass
    12.
    发明授权
    Method of shaping sheet glass 失效
    成型玻璃板的方法

    公开(公告)号：US06668589B1

    公开(公告)日：2003-12-30

    申请号：US08858116

    申请日：1997-05-19

    Applicant: Tetsuya Mizusugi ,  Kazunori Yuki ,  Mitsuo Tanaka

    Inventor： Tetsuya Mizusugi ,  Kazunori Yuki ,  Mitsuo Tanaka

    IPC: C03B23035

    CPC classification number: C03B23/0357

    Abstract: A suction mold has a central suction chamber having a flat shaping surface area and a pair of opposite side suction chambers disposed one on each side of the central suction chamber and having respective curved shaping surface areas. First, a vacuum is developed in the central suction chamber to attract a central area of the sheet of glass against the flat shaping surface area thereof, and then a vacuum is developed in the opposite side suction chambers to attract opposite side areas of the sheet of glass respectively against the curved shaping surface areas.

    Abstract translation: 抽吸模具具有中央抽吸室，其具有平坦的成形表面区域和一对相对的侧吸入室，该吸入室设置在中央抽吸室的每一侧上并且具有相应的弯曲成形表面区域。 首先，在中央抽吸室中产生真空以吸引玻璃板的中心区域抵靠其平坦成形表面区域，然后在相对侧的吸入室中产生真空以吸引该片材的相对侧面区域 玻璃分别对着弯曲的成形表面区域。

    Rotary connector for connecting cables
    14.
    发明授权
    Rotary connector for connecting cables 失效
    用于连接电缆的旋转连接器

    公开(公告)号：US6007355A

    公开(公告)日：1999-12-28

    申请号：US928503

    申请日：1997-09-12

    Applicant: Masahiro Shibata ,  Mitsuo Tanaka ,  Ryusaku Koike

    Inventor： Masahiro Shibata ,  Mitsuo Tanaka ,  Ryusaku Koike

    IPC: B60R16/02 ,  B60R16/027 ,  H01H85/20 ,  H01R13/68 ,  H01R35/02 ,  H01R35/04

    CPC classification number: B60R16/027 ,  H01R35/025 ,  H01H85/201

    Abstract: A rotary connector configured so as to enable extension or contraction of a cable transmitting electrical signals etc. by connecting a spirally wound flat cable between two cable parts and making the spirally wound flat cable wind or unwind using a rotary body and a fixed body, more particularly a rotary connector able to protect the flat cable from fusing when an overcurrent flows. The plus side connection portion of connection portions between conductors of a flat cable and an outer conductor (cable) electrically connects the conductors of the flat cable and the outer conductor through members having a fuse function. When a short-circuit occurs in the circuit including the flat cable and the outer conductor, the member having a fuse function fuses first so as to prevent the flat cable from heating and fusing.

    Abstract translation: 一种旋转连接器，其被构造成能够通过将螺旋卷绕的扁平电缆连接在两个电缆部件之间并使螺旋卷绕的扁平电缆使用旋转体和固定体进行卷绕或展开，从而能够延伸或收缩传输电信号的电缆等。 特别是能够在过电流流动时保护扁平电缆不熔断的旋转连接器。 扁平电缆的导体和外部导体（电缆）的导体之间的连接部分的正面连接部分通过具有保险丝功能的部件电连接扁平电缆的导体和外部导体。 当包括扁平电缆和外部导体在内的电路发生短路时，具有保险丝功能的部件首先熔断，以防止扁平电缆加热和熔断。

    Semiconductor Bi-MIS device
    15.
    发明授权
    Semiconductor Bi-MIS device 失效
    半导体Bi-MIS器件

    公开(公告)号：US5838048A

    公开(公告)日：1998-11-17

    申请号：US915327

    申请日：1997-08-20

    Applicant: Takehiro Hirai ,  Masahiro Nakatani ,  Mitsuo Tanaka ,  Akihiro Kanda

    Inventor： Takehiro Hirai ,  Masahiro Nakatani ,  Mitsuo Tanaka ,  Akihiro Kanda

    IPC: H01L21/8249 ,  H01L27/06 ,  H01L29/51 ,  H01L27/02 ,  H01L29/68

    CPC classification number: H01L29/513 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/518 ,  Y10S148/009

    Abstract: A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.

    Abstract translation: 在硅衬底上形成氧化硅膜和多晶硅膜，并且被选择性地蚀刻以在要形成发射极的区域中形成接触孔。 将多晶硅膜放置在衬底上，并且将两个多晶硅膜图案化以形成由掺杂有砷的两个多晶硅膜制成的发射极电极和栅极电极。 砷从发射电极的多晶硅膜扩散到硅衬底中以形成具有高浓度且浅的N +发射极层。 因此，可以防止栅极绝缘膜的污染，并且可以形成具有高性能的双极晶体管，例如高电流放大因子等。

    Electrical connection box
    16.
    发明授权
    Electrical connection box 失效
    电气接线盒

    公开(公告)号：US5761038A

    公开(公告)日：1998-06-02

    申请号：US655706

    申请日：1996-05-30

    Applicant: Mitsuo Tanaka

    Inventor： Mitsuo Tanaka

    IPC: B60R16/02 ,  B60R16/023 ,  H05K7/02 ,  H05K7/20 ,  H02B1/26

    CPC classification number: B60R16/0239 ,  H05K7/026

    Abstract: An electrical connection box having heat generating electrical parts contained therein includes an upper case, a case body, and a lower case. The case body has a top surface on which numerous concave grooves are formed in a matrix shape, and at least one of the concave grooves receives a cooling device therein in such a manner that a heat absorbing side of the cooling device is positioned inside the electrical connection box and a heat radiating side of the cooling device is located outside of the electrical connection box. Alternatively, the case body may include numerous attaching holes formed in a thickness direction of the case body or in a direction perpendicular to the thickness direction of the case body, and at least one of the attaching holes receives a cooling device therein in such a manner that a heat absorbing side of the cooling device is positioned inside the electrical connection box and a heat radiating side of the cooling device is located outside of the electrical connection box. A position of the cooling device is capable of being changed in accordance with given mounting positions of the heat generating electrical parts.

    Abstract translation: 其中容纳有发热电气部件的电连接盒包括上壳体，壳体和下壳体。 壳体具有顶面，多个凹槽形成为矩阵形状，并且至少一个凹槽在其中容纳冷却装置，使得冷却装置的吸热侧位于电气的内部 连接箱和冷却装置的散热侧位于电气接线盒的外部。 或者，壳体可以包括在壳体的厚度方向上形成的许多附接孔或者与壳体的厚度方向垂直的方向，并且至少一个安装孔以这种方式容纳冷却装置 冷却装置的吸热侧位于电连接箱的内部，并且冷却装置的散热侧位于电连接箱的外部。 冷却装置的位置能够根据发热电气部件的给定安装位置而改变。

    Semiconductor Bi-MIS device and method of manufacturing the same
    18.
    发明授权
    Semiconductor Bi-MIS device and method of manufacturing the same 失效
    半导体Bi-MIS器件及其制造方法

    公开(公告)号：US5406106A

    公开(公告)日：1995-04-11

    申请号：US76838

    申请日：1993-06-15

    Applicant: Takehiro Hirai ,  Masahiro Nakatani ,  Mitsuo Tanaka ,  Akihiro Kanda

    Inventor： Takehiro Hirai ,  Masahiro Nakatani ,  Mitsuo Tanaka ,  Akihiro Kanda

    IPC: H01L21/8249 ,  H01L27/06 ,  H01L29/51 ,  H01L27/02 ,  H01L27/04 ,  H01L29/68

    CPC classification number: H01L29/513 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/518

    Abstract: A silicon oxide film as a dielectric film and a silicon nitride film or a polysilicon film as a protection film for the silicon oxide film are formed on a silicon substrate. After the two films are selectively etched to form contact holes of a bipolar transistor, a polysilicon film as a conductive film is laid on the entire substrate and selectively etched to form electrodes. In a MIS transistor, the protection film of the silicon nitride film serves as a gate insulator film and the protection film of the polysilicon film serves as a gate electrode. Accordingly, contamination to the gate insulator film at formation of contact holes of the bipolar transistor is prevented, and an excellent semiconductor with Bi-MOS structure is manufactured with low cost.

    Abstract translation: 在硅衬底上形成作为电介质膜的氧化硅膜和作为氧化硅膜保护膜的氮化硅膜或多晶硅膜。 在选择性地蚀刻两个膜以形成双极晶体管的接触孔之后，将作为导电膜的多晶硅膜铺设在整个基板上并选择性地蚀刻以形成电极。 在MIS晶体管中，氮化硅膜的保护膜用作栅极绝缘膜，多晶硅膜的保护膜用作栅电极。 因此，防止了在形成双极晶体管的接触孔时对栅极绝缘膜的污染，并以低成本制造了具有Bi-MOS结构的优良半导体。

    Semiconductor device including integrated injection logic and vertical NPN and PNP transistors
    19.
    发明授权
    Semiconductor device including integrated injection logic and vertical NPN and PNP transistors 失效
    半导体器件包括集成注入逻辑和垂直NPN和PNP晶体管

    公开(公告)号：US5323054A

    公开(公告)日：1994-06-21

    申请号：US907470

    申请日：1992-07-01

    Applicant: Akihiro Kanda ,  Mitsuo Tanaka ,  Takehiro Hirai ,  Masahiro Nakatani

    Inventor： Akihiro Kanda ,  Mitsuo Tanaka ,  Takehiro Hirai ,  Masahiro Nakatani

    IPC: H01L21/74 ,  H01L21/8226 ,  H01L27/082 ,  H01L29/165 ,  H01L29/700

    CPC classification number: H01L21/8226 ,  H01L21/743 ,  H01L27/0826

    Abstract: In a a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same substrate, grooves that reach an n.sup.+ -type buried layer 5 serving as an emitter of the IIL and an n.sup.+ -type buried layer 4 serving as a collector of the vertical npn transistor are formed at the same time, and an oxide film 101 is formed only on the sidewall of each groove; in the grooves, n.sup.+ -type polycrystalline silicon films 103 and 102 are formed, which are made to serve as an emitter lead-out portion of the IIL and a collector wall of the vertical npn transistor, respectively; a p-type diffused layer 17 serving as an injector of the IIL and a p-type diffused layer 18 and p.sup.- -type diffused layer 12 serving as the base thereof are respectively so formed as to be adjoining to the oxide film 101 of the emitter lead-out portion of the IIL; and a p-type diffused layer 16 serving as the base of the vertical npn transistor is so formed as to be adjoining to the oxide film 101 of the collecter wall. The semiconductor device can achieve a smaller cell size, a decrease in parasitic capacitance and an increase in operating speed.

    Abstract translation: 在具有垂直npn晶体管，集成在同一衬底上的垂直pnp晶体管和IIL的半导体器件中，到达用作IIL的发射极的n +型掩埋层5和n +型掩埋层4的沟槽 同时形成垂直npn晶体管的集电极，只在每个沟槽的侧壁上形成氧化膜101; 在凹槽中形成n +型多晶硅膜103和102，它们分别用作IIL的发射极引出部分和垂直npn晶体管的集电壁; 用作IIL的注射器的p型扩散层17和作为其基底的p型扩散层18和p型扩散层12分别形成为邻接于 发射极引出部分; 并且用作垂直npn晶体管的基极的p型扩散层16形成为与收集器壁的氧化物膜101相邻。 半导体器件可以实现更小的单元尺寸，寄生电容的减小和操作速度的增加。

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