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    Method and apparatus for performing select operations
    12.
    发明申请
    Method and apparatus for performing select operations 审中-公开
    用于执行选择操作的方法和装置

    公开(公告)号：US20080077772A1

    公开(公告)日：2008-03-27

    申请号：US11526065

    申请日：2006-09-22

    Applicant: Ronen Zohar ,  Mohammad Abdallah ,  Boris Sabanin ,  Mark Seconi

    Inventor： Ronen Zohar ,  Mohammad Abdallah ,  Boris Sabanin ,  Mark Seconi

    IPC: G06F9/30

    CPC classification number: G06F9/30112 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30138 ,  G06F9/30185

    Abstract: A method and apparatus for including in a processor instructions for performing select operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein first packed data in a source operand and a second packed data in a destination operand. The processor selects the first packed data if the control bit for the source operand is set to “1” and stores the data into the destination operand. Otherwise, the processor keeps the data in the destination operand. The final value of the destination operand is stored in memory.

    Abstract translation: 一种用于在处理器中包括用于对打包或未打包的数据执行选择操作的指令的方法和装置。 在一个实施例中，处理器耦合到存储器。 存储器中存储有源操作数中的第一打包数据和目的地操作数中的第二打包数据。 如果源操作数的控制位设置为“1”，则处理器选择第一打包数据，并将数据存储到目标操作数中。 否则，处理器将数据保存在目标操作数中。 目标操作数的最终值存储在内存中。

    Executing partial-width packed data instructions
    13.
    发明授权
    Executing partial-width packed data instructions 有权
    执行部分宽度打包的数据指令

    公开(公告)号：US06970994B2

    公开(公告)日：2005-11-29

    申请号：US09852217

    申请日：2001-05-08

    Applicant: Mohammad Abdallah ,  James Coke ,  Vladimir Pentkovski ,  Patrice Roussel ,  Shreekant S. Thakkar

    Inventor： Mohammad Abdallah ,  James Coke ,  Vladimir Pentkovski ,  Patrice Roussel ,  Shreekant S. Thakkar

    IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318

    CPC classification number: G06F9/3875 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30196 ,  G06F9/384 ,  G06F9/3885

    Abstract: A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. The first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, the second set of instructions specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either of the first or the second set of instructions.

    Abstract translation: 讨论了用于执行部分宽度打包数据指令的方法和装置。 处理器可以包括多个寄存器，寄存器重命名单元，解码器和部分宽度执行单元。 寄存器重命名单元提供架构寄存器文件以存储打包数据操作数，每个数据操作数包括多个数据元素。 解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。 第一组指令指定要对存储在一个或多个指定寄存器中的所有数据元素执行的操作。 相比之下，第二组指令指定仅对数据元素的子集执行的操作。 部分宽度执行单元是执行由第一组或第二组指令指定的操作。

    Single cycle multi-branch prediction including shadow cache for early far branch prediction
    14.
    发明授权
    Single cycle multi-branch prediction including shadow cache for early far branch prediction 有权

    公开(公告)号：US10228949B2

    公开(公告)日：2019-03-12

    申请号：US13824013

    申请日：2011-09-16

    Applicant: Mohammad Abdallah

    Inventor： Mohammad Abdallah

    IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

    Abstract: A method of identifying instructions including accessing a plurality of instructions that comprise multiple branch instructions. For each branch instruction of the multiple branch instructions, a respective first mask is generated representing instructions that are executed if a branch is taken. A respective second mask is generated representing instructions that are executed if the branch is not taken. A prediction output is received that comprises a respective branch prediction for each branch instruction. For each branch instruction, the prediction output is used to select a respective resultant mask from among the respective first and second masks. For each branch instruction, a resultant mask of a subsequent branch is invalidated if a previous branch is predicted to branch over said subsequent branch. A logical operation is performed on all resultant masks to produce a final mask. The final mask is used to select a subset of instructions for execution.

    Integer rounding operation
    17.
    发明授权
    Integer rounding operation 有权
    整数舍入操作

    公开(公告)号：US08732226B2

    公开(公告)日：2014-05-20

    申请号：US11447344

    申请日：2006-06-06

    Applicant: Mohammad Abdallah ,  Chad D. Hancock ,  Kwok W. Lui

    Inventor： Mohammad Abdallah ,  Chad D. Hancock ,  Kwok W. Lui

    IPC: G06F7/38 ,  G06F7/499

    CPC classification number: G06F7/49947 ,  G06F7/483 ,  G06F7/49915 ,  G06F7/49963 ,  G06F9/30014 ,  G06F9/30036

    Abstract: Systems, methods, processors, media, and other embodiments associated with integer rounding a floating point number in one micro-operation (uop) are described. One system embodiment includes a memory to store an integer rounding floating point instruction and a processor to perform the integer rounding floating point instruction. The processor may include a floating point unit that includes circuits and/or logics that integer round the floating point number.

    Abstract translation: 描述了在一个微操作（uop）中与整数舍入浮点数相关联的系统，方法，处理器，介质和其他实施例。 一个系统实施例包括存储整数舍入浮点指令的存储器和执行整数舍入浮点指令的处理器。 处理器可以包括浮点单元，其包括围绕浮点数整数的电路和/或逻辑。

    SYSTEMS AND METHODS FOR NON-BLOCKING IMPLEMENTATION OF CACHE FLUSH INSTRUCTIONS
    18.
    发明申请
    SYSTEMS AND METHODS FOR NON-BLOCKING IMPLEMENTATION OF CACHE FLUSH INSTRUCTIONS 有权
    缓存缓存指令的非阻塞实现的系统和方法

    公开(公告)号：US20140108730A1

    公开(公告)日：2014-04-17

    申请号：US13649532

    申请日：2012-10-11

    Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

    Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

    IPC: G06F12/08

    CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0837 ,  G06F12/0897 ,  G06F2212/1024

    Abstract: Systems and methods for non-blocking implementation of cache flush instructions are disclosed. As a part of a method, data is accessed that is received in a write-back data holding buffer from a cache flushing operation, the data is flagged with a processor identifier and a serialization flag, and responsive to the flagging, the cache is notified that the cache flush is completed. Subsequent to the notifying, access is provided to data then present in the write-back data holding buffer to determine if data then present in the write-back data holding buffer is flagged.

    Abstract translation: 公开了用于非阻塞实现高速缓存刷新指令的系统和方法。 作为方法的一部分，从高速缓存刷新操作访问在回写数据保持缓冲器中接收的数据，数据用处理器标识符和串行化标志标记，并且响应于标记，高速缓存被通知 高速缓存刷新完成。 在通知之后，将访问提供给然后存在于写回数据保持缓冲器中的数据，以确定是否标记了在回写数据保持缓冲器中存在的数据。

    HARDWARE ACCELERATION COMPONENTS FOR TRANSLATING GUEST INSTRUCTIONS TO NATIVE INSTRUCTIONS
    19.
    发明申请
    HARDWARE ACCELERATION COMPONENTS FOR TRANSLATING GUEST INSTRUCTIONS TO NATIVE INSTRUCTIONS 有权
    硬件加速组件用于将用户说明转换为本指令

    公开(公告)号：US20130024661A1

    公开(公告)日：2013-01-24

    申请号：US13360024

    申请日：2012-01-27

    Applicant: Mohammad Abdallah

    Inventor： Mohammad Abdallah

    IPC: G06F9/312

    CPC classification number: G06F9/30174 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30098 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/3867 ,  G06F9/3879 ,  G06F9/45516 ,  G06F12/0875 ,  G06F15/8007 ,  G06F2212/452

    Abstract: A hardware based translation accelerator. The hardware includes a guest fetch logic component for accessing guest instructions; a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling guest instructions into a guest instruction block; and conversion tables coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block. The hardware further includes a native cache coupled to the conversion tables for storing the corresponding native conversion block, and a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block, wherein upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache.

    Abstract translation: 一种基于硬件的翻译加速器。 硬件包括用于访问访客指令的访客提取逻辑组件; 耦合到客户提取逻辑组件的访客提取缓冲器和用于将访客指令组装到访客指令块中的分支预测组件; 以及耦合到访客提取缓冲器的转换表，用于将访客指令块转换为相应的本机转换块。 硬件还包括耦合到用于存储对应的本机转换块的转换表的本地高速缓存，以及耦合到本地高速缓存的转换看待缓冲器，用于存储客户指令块到对应的本机转换块的映射，其中在随后的 请求访客指令，转换看待缓冲区被索引以确定是否发生命中，其中映射指示客户指令在本机高速缓存中具有对应的转换的本地指令。

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