公开(公告)号：US20120139575A1

公开(公告)日：2012-06-07

申请号：US13068152

申请日：2011-03-10

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/26

CPC classification number: G01R31/2884 ,  G01R31/2851 ,  G01R31/2853 ,  G01R31/2855

Abstract: An apparatus, suitable for coupling a pads of integrated circuits on wafer to the pogo pins of a pogo tower in a test system without the need of a probe card, includes a body having a first surface and a second surface, the body having a substantially circular central portion, and a plurality of bendable arms extending outwardly from the central portion, each bendable arm having a connector tab disposed at the distal end thereof; a first plurality of contact terminals disposed on the second surface of the central portion of the body, the first plurality of contact terminals arranged in pattern to match the layout of pads on a wafer to be contacted; at least one contact terminal disposed on the first surface of the plurality of connector tabs; and a plurality of electrically conductive pathways disposed in the body such that each of the first plurality of contact terminals is electrically connected to a corresponding one of the contact terminals on the first surface of the connector tabs.

Abstract translation: 一种适于将晶片上的集成电路的焊盘与测试系统中的浮标塔的弹簧销耦合而不需要探针卡的装置包括具有第一表面和第二表面的本体，该主体具有基本上 圆形中心部分和从中心部分向外延伸的多个可弯曲臂，每个可弯曲臂具有设置在其远端处的连接片; 设置在所述主体的中心部分的第二表面上的第一多个接触端子，所述第一多个接触端子以图案布置以匹配待接触的晶片上的焊盘的布局; 至少一个接触端子，设置在所述多个连接器接头的第一表面上; 以及设置在所述主体中的多个导电通路，使得所述第一多个接触端子中的每一个电连接到所述连接器接头的第一表面上的对应的一个接触端子。

公开(公告)号：US07723980B2

公开(公告)日：2010-05-25

申请号：US12079159

申请日：2008-03-24

Applicant: Morgan T. Johnson ,  Raymond J. Werner

Inventor： Morgan T. Johnson ,  Raymond J. Werner

IPC: G01R31/02 ,  G01R31/26

CPC classification number: G01R31/2884 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for producing fully tested unsingulated integrated circuits without probe scrub damage to bond pads includes forming a wafer/wafer translator pair removably attached to each other wherein the wafer translator includes contact structures formed from a soft crushable electrically conductive material and these contact structures are brought into contact with the bond pads in the presence of an inert gas; and subsequently a vacuum is drawn between the wafer and the wafer translator. In one aspect of the present invention, the unsingulated integrated circuits are exercised by a plurality of test systems wherein the bond pads are never physically touched by the test system and electrical access to the wafer is only provided through the inquiry-side of the wafer translator. In a further aspect of the present invention, known good die having bond pads without probe scrub marks are provided for incorporation into products.

Abstract translation: 用于生产完全被测试的非镶嵌集成电路的方法和装置，不对接合焊盘进行探针磨损损伤包括形成可移除地彼此附接的晶片/晶片转换器对，其中晶片转换器包括由软的可压电导电材料形成的接触结构，并且这些接触结构 在惰性气体存在下与接合垫接触; 随后在晶片和晶片转换器之间抽真空。 在本发明的一个方面中，由多个测试系统来执行无调制的集成电路，其中接合焊盘从未被测试系统物理地接触，并且仅通过晶片转换器的查询侧提供对晶片的电接触 。 在本发明的另一方面，提供了具有不具有探针擦洗痕的接合垫的已知的良好的模头用于结合到产品中。

公开(公告)号：US07719298B2

公开(公告)日：2010-05-18

申请号：US12272717

申请日：2008-11-17

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02

CPC classification number: G01R31/2863 ,  G01R31/2875

Abstract: Assemblies include a substrate, such as a printed circuit board, with a first array of contact pads disposed thereon; a guide ring structure disposed on the substrate and at least partially surrounding the first array of contact pads; a translator socket disposed on the first array of contact pads, the translator socket adapted to receive the tester side of a translated wafer; a thermally conductive, conformal, heat spreading cushion adapted to be disposed over the backside of a wafer; a cover plate adapted to fit over the first array of contact pads, align with the guide ring structure, contain within it the various components disposed over the first array of contact pads, and removably attach to the substrate; and a bolster plate adapted to removably attach to a second side of the substrate. In a further aspect a translated wafer is disposed over the translator socket such that the tester side of the translator is in contact with the translator socket; and the heat spreading cushion is disposed over the backside of the translated wafer. In a still further aspect, the substrate includes signal communication means, such as but not limited to, an edge connector adapted to couple to various controller circuits, which are typically disposed on a printed circuit board.

Abstract translation: 组件包括衬底，例如印刷电路板，其上布置有第一阵列的接触焊盘; 引导环结构，其设置在所述基板上并且至少部分地围绕所述第一接触焊盘阵列; 设置在所述第一接触焊盘阵列上的转换器插座，所述转换器插座适于接收翻译的晶片的测试器侧; 适于设置在晶片的背面上方的导热的，共形的散热垫; 适于装配在所述第一接触焊盘阵列上的盖板，与所述引导环结构对准，在其中包含设置在所述第一接触焊盘阵列上的各种部件，并且可移除地附接到所述衬底; 以及适于可拆卸地附接到基底的第二侧的枕板。 在另一方面，翻译的晶片设置在翻译器插座上方，使得翻译器的测试器侧与翻译器插座接触; 并且散热垫设置在翻译的晶片的背面上。 在另一方面，衬底包括信号通信装置，例如但不限于适于耦合到通常设置在印刷电路板上的各种控制器电路的边缘连接器。

公开(公告)号：US20100033203A1

公开(公告)日：2010-02-11

申请号：US12365895

申请日：2009-02-04

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/26

CPC classification number: G01R31/286

Abstract: A translated wafer stand-in tester, being a hybrid apparatus capable of emulating the form factor and some or all behaviors of a translated wafer under test, which is operable to store, quantify, encode and convey, either directly or remotely, data from a testing system, including but not limited to pad pressure, electrical contact and temperature. The translated wafer stand-in tester may include several stacked and attached layers, at least one internal layer including electronic components operable to interact with a test system.

Abstract translation: 一种翻译的晶片待机测试仪，其是能够模拟被测翻译的晶片的形状因子和一些或所有行为的混合设备，其可操作以直接或远程地存储，量化，编码和传送来自 测试系统，包括但不限于焊盘压力，电接触和温度。 翻译的晶片待机测试器可以包括几个堆叠和附接的层，至少一个内层，包括可操作以与测试系统相互作用的电子组件。

公开(公告)号：US20090284274A1

公开(公告)日：2009-11-19

申请号：US12272717

申请日：2008-11-17

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02 ,  G01R31/26

CPC classification number: G01R31/2863 ,  G01R31/2875

Abstract: Assemblies include a substrate, such as a printed circuit board, with a first array of contact pads disposed thereon; a guide ring structure disposed on the substrate and at least partially surrounding the first array of contact pads; a translator socket disposed on the first array of contact pads, the translator socket adapted to receive the tester side of a translated wafer; a thermally conductive, conformal, heat spreading cushion adapted to be disposed over the backside of a wafer; a cover plate adapted to fit over the first array of contact pads, align with the guide ring structure, contain within it the various components disposed over the first array of contact pads, and removably attach to the substrate; and a bolster plate adapted to removably attach to a second side of the substrate. In a further aspect a translated wafer is disposed over the translator socket such that the tester side of the translator is in contact with the translator socket; and the heat spreading cushion is disposed over the backside of the translated wafer. In a still further aspect, the substrate includes signal communication means, such as but not limited to, an edge connector adapted to couple to various controller circuits, which are typically disposed on a printed circuit board.

Abstract translation: 组件包括衬底，例如印刷电路板，其上布置有第一阵列的接触焊盘; 引导环结构，其设置在所述基板上并且至少部分地围绕所述第一接触焊盘阵列; 设置在所述第一接触焊盘阵列上的转换器插座，所述转换器插座适于接收翻译的晶片的测试器侧; 适于设置在晶片的背面上方的导热的，共形的散热垫; 适于装配在所述第一接触焊盘阵列上的盖板，与所述引导环结构对准，在其中包含设置在所述第一接触焊盘阵列上的各种部件，并且可移除地附接到所述衬底; 以及适于可拆卸地附接到基底的第二侧的枕板。 在另一方面，翻译的晶片设置在翻译器插座上方，使得翻译器的测试器侧与翻译器插座接触; 并且散热垫设置在翻译的晶片的背面上。 在另一方面，衬底包括信号通信装置，例如但不限于适于耦合到通常设置在印刷电路板上的各种控制器电路的边缘连接器。

公开(公告)号：US07459924B2

公开(公告)日：2008-12-02

申请号：US11825567

申请日：2007-07-06

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02

CPC classification number: G01R1/07342 ,  G01R31/2886

Abstract: Concurrent electrical access to the pads of integrated circuits on a wafer is provided by an edge-extended wafer translator that carries signals from one or more pads on one or more integrated circuits to contact terminals on the inquiry-side of the edge-extended wafer translator, including portions of the inquiry-side that are superjacent the wafer when the wafer and the edge-extended wafer translator are in a removably attached state, and portions of the inquiry side that reside outside a region defined by the intersection of the wafer and the edge-extended wafer translator. In a further aspect of the present invention, access to the pads of integrated circuits on a wafer is additionally provided by contact terminals in a second inquiry area located on the wafer-side of the edge-extended wafer translator in a region thereof bounded by its outer circumference and the circumference of the attached wafer.

Abstract translation: 通过边缘扩展晶片转换器提供对晶片上的集成电路的焊盘的并发电接口，其将信号从一个或多个集成电路上的一个或多个焊盘传送到边缘扩展晶片转换器的查询侧的接触端子 包括当晶片和边缘延伸晶片转换器处于可移除地附接状态时位于晶片上方的询问侧的部分以及位于由晶片和边缘延伸晶片转换器的相交处限定的区域之外的查询侧的部分 边缘延伸晶片转换器。 在本发明的另一方面，在位于边缘延伸晶片转换器的晶片侧的第二查询区域中的接触端子附加地提供对晶片上的集成电路焊盘的访问，该区域由其边界 外圆周和圆周。

公开(公告)号：US20080273847A1

公开(公告)日：2008-11-06

申请号：US12154684

申请日：2008-05-24

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G02B6/04

CPC classification number: G02B6/4222 ,  G01R31/2891 ,  G02B6/04 ,  G02B6/4226 ,  G02B6/4227

Abstract: A low-cost alignment system suitable for aligning a wafer to a test fixture includes a bundle of optical fibers wherein at least one fiber serves to deliver illumination to the alignment target from an end thereof, and a plurality of receiver fibers, each having ends with a known spatial relationship to the end of the illuminator fiber. The ends of the fiber bundle have a known spatial relationship to the fixture. In some embodiments, the fiber bundle is disposed within the fixture such that there is an unobscured optical path between the wafer and the receiving and illuminating ends of the fibers. In some embodiments, the fiber bundle is coupled to a light source and a light sensor mounted on the fixture. In some embodiments the alignment target is one or more bonding pads disposed on a wafer.

Abstract translation: 适用于将晶片对准测试夹具的低成本对准系统包括一束光纤，其中至少一根光纤用于从其端部向对准目标物发射照明，以及多个接收器光纤，每个接收器光纤 与照明器光纤末端的已知空间关系。 纤维束的端部与夹具具有已知的空间关系。 在一些实施例中，纤维束设置在固定装置内，使得在晶片与纤维的接收和照射端之间存在视觉上的光路。 在一些实施例中，光纤束耦合到安装在固定装置上的光源和光传感器。 在一些实施例中，对准靶是设置在晶片上的一个或多个接合焊盘。

公开(公告)号：US20070296449A1

公开(公告)日：2007-12-27

申请号：US11810237

申请日：2007-06-05

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/26

CPC classification number: G01R1/07342 ,  G01R31/2886

Abstract: Access to integrated circuits of a wafer for concurrently performing two or more types of testing, is provided by bringing a wafer and an edge-extended wafer translator into an attached state. The edge-extended wafer translator having wafer-side contact terminals and inquiry-side contact terminals disposed thereon, a first set of wafer-side contact terminals being electrically coupled to a first set of inquiry-side contact terminals, and a second set of wafer-side contact terminals being electrically coupled to a second set of inquiry-side contact terminals. The edge-extended wafer translator having a central portion generally coextensive with the attached wafer, and an edge-extended portion extending beyond the boundary generally defined by the outer circumferential edge of the wafer. A first set of pads of at least one integrated circuit is electrically coupled to the first set of wafer-side contact terminals, and a second set of pads of the integrated circuit is electrically coupled to the second set of wafer-side contact terminals. The edge-extended wafer translator may be shaped such that its edge-extended portion is not coplanar with the central portion thereof.

Abstract translation: 通过使晶片和边缘延伸的晶片转换器进入附接状态来提供对晶片的集成电路的访问以同时执行两种或更多种类型的测试。 边缘延伸晶片转换器具有设置在其上的晶片侧接触端子和询问侧接触端子，第一组晶片侧接触端子电耦合到第一组查询侧接触端子，以及第二组晶片 侧接触端子电耦合到第二组询问侧接触端子。 边缘延伸晶片转换器具有与附接的晶片大致共同延伸的中心部分，以及延伸超出通常由晶片的外圆周边缘限定的边界的边缘延伸部分。 至少一个集成电路的第一组焊盘电耦合到第一组晶片侧接触端子，并且集成电路的第二组焊盘电耦合到第二组晶片侧接触端子。 边缘延伸晶片转换器可以被成形为使得其边缘延伸部分不与其中心部分共面。

公开(公告)号：US06994918B2

公开(公告)日：2006-02-07

申请号：US10917029

申请日：2004-08-11

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: B32B15/00 ,  H05K7/10

CPC classification number: H05K3/4015 ,  H05K3/027 ,  H05K3/341 ,  H05K2203/0191 ,  H05K2203/0769 ,  H05K2203/0786 ,  Y10T428/12493 ,  Y10T428/12507 ,  Y10T428/12514

Abstract: A component for use in manufacturing circuit boards, such as printed circuit boards, or flex substrates is adapted for use with pick-and-place equipment to provide a first material overlay disposed over a second material base layer. Such a component may include a first electrically conductive material disposed over a second electrically conductive material, and a soluble tape backing disposed over and attached to the second electrically conductive material. The component may be attached to a circuit board by solder relow, after which the soluble tape backing is removed. Although typical embodiments involve electrically conductive materials, it is noted that an electrically insulating material can also be disposed over and attached to an underlying material which itself is disposed on a circuit board.

Abstract translation: 用于制造电路板（例如印刷电路板或柔性基板）的部件适于与拾取和放置设备一起使用，以提供设置在第二材料基层上的第一材料覆盖层。 这样的部件可以包括设置在第二导电材料上的第一导电材料和设置在第二导电材料上并附着到第二导电材料上的可溶性带背。 组件可以通过焊料回流连接到电路板，然后除去可溶性胶带背衬。 虽然典型的实施例涉及导电材料，但应注意的是，电绝缘材料也可以设置在本身设置在电路板上的下层材料上并附着于其上。

公开(公告)号：US09052355B2

公开(公告)日：2015-06-09

申请号：US13068158

申请日：2011-03-10

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/00 ,  G01R31/28 ,  G01R1/073

CPC classification number: G01R1/07371 ,  G01R1/04 ,  G01R1/0408 ,  G01R1/07314 ,  G01R1/07342 ,  G01R31/2887 ,  G01R31/2889

Abstract: Methods and apparatus for testing unsingulated integrated circuits on a wafer include adapting a wafer prober for use with full-wafer-contacter disposed on the wafer. Some embodiments include placing wafer on a chuck of the prober, aligning the wafer to a full-wafer contacter incorporated in the wafer prober, removably attaching the wafer to the full wafer contacter, separating the wafer from the chuck, and making electrical contact to one or more integrated circuits of the wafer by making physical contact with a surface of the full-wafer contacter that faces away from the wafer.

Abstract translation: 用于测试晶片上的非镶嵌集成电路的方法和装置包括使晶片探针适配用于设置在晶片上的全晶圆封装。 一些实施例包括将晶片放置在探测器的卡盘上，将晶片对准结晶在晶圆探针中的全晶圆接头，将晶片可移除地附接到全晶片连接器，将晶片与卡盘分离，并将电接触到一个 或更多的集成电路，通过与全晶圆连接器的远离​​晶片的表面进行物理接触。