公开(公告)号：US20070281442A1

公开(公告)日：2007-12-06

申请号：US11812030

申请日：2007-06-14

Applicant: Munaf Rahimo ,  Arnost Kopta ,  Stefan Linder

Inventor： Munaf Rahimo ,  Arnost Kopta ,  Stefan Linder

IPC: H01L21/30

CPC classification number: H01L29/66333 ,  H01L29/0834 ,  H01L29/7395

Abstract: In order to produce a power semiconductor for operation at high blocking voltages, there is produced on a lightly doped layer having a doping of a first charge carrier type a medium-doped layer of the same charge carrier type. A highly doped layer is produced at that side of the medium-doped layer which is remote from the lightly doped layer, of which highly doped layer a part with high doping that remains in the finished semiconductor forms a second stop layer, wherein the doping of the highly doped layer is higher than the doping of the medium-doped layer. An electrode is subsequently indiffused into the highly doped layer. The part with low doping that remains in the finished semiconductor forms the drift layer and the remaining medium-doped part forms the first stop layer.

Abstract translation: 为了产生用于在高阻挡电压下操作的功率半导体，在具有掺杂第一电荷载体类型的相同电荷载流子型的中等掺杂层的轻掺杂层上产生。 在远离轻掺杂层的介质掺杂层的该侧产生高掺杂层，其中高掺杂层保留在最终半导体中的具有高掺杂的部分形成第二阻挡层，其中掺杂 高掺杂层比掺杂中掺杂层高。 随后将电极扩散到高掺杂层中。 保留在成品半导体中的低掺杂部分形成漂移层，剩余的中等掺杂部分形成第一停止层。

公开(公告)号：US20070158686A1

公开(公告)日：2007-07-12

申请号：US10579837

申请日：2004-11-16

Applicant: Munaf Rahimo ,  Stefan Linder

Inventor： Munaf Rahimo ,  Stefan Linder

IPC: H01L31/00 ,  H01L29/739

CPC classification number: B67D1/1422 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/7395

Abstract: In an insulated gate bipolar transistor, an improved safe operating area capability is achieved according to the invention by a two-fold base region comprising a first base region (81), which is disposed in the channel region (7) so that it encompasses the one or more source regions (6), but does not adjoin the second main surface underneath the gate oxide layer (41), and a second base region (82) is disposed in the semiconductor substrate (2) underneath the base contact area (821) so that it partially overlaps with the channel region (7) and with the first base region (81).

Abstract translation: 在绝缘栅双极晶体管中，根据本发明，通过包括设置在沟道区域（7）中的第一基极区域（81）的双折叠基极区域实现改进的安全工作面积能力，使得其包围 一个或多个源极区域（6），但不与栅极氧化物层（41）下面的第二主表面相邻，并且第二基极区域（82）设置在基极接触区域（821）下面的半导体衬底 ），使得其与沟道区域（7）和第一基极区域（81）部分重叠。

公开(公告)号：US09654085B2

公开(公告)日：2017-05-16

申请号：US14358103

申请日：2011-11-22

Applicant: Falah Hosini ,  Madhan Mohan ,  Siva Nagi Reddy Pamulapati ,  Arnost Kopta ,  Munaf Rahimo ,  Raffael Schnell ,  Ulrich Schlapbach

Inventor： Falah Hosini ,  Madhan Mohan ,  Siva Nagi Reddy Pamulapati ,  Arnost Kopta ,  Munaf Rahimo ,  Raffael Schnell ,  Ulrich Schlapbach

IPC: H03K3/00 ,  H03K3/012 ,  H03K17/0812 ,  H03K17/082 ,  H03K17/18 ,  H03K17/567

CPC classification number: H03K3/012 ,  H03K17/08128 ,  H03K17/0828 ,  H03K17/18 ,  H03K17/567 ,  H03K2217/0027 ,  H03K2217/0036

Abstract: A reverse-conducting insulated gate bipolar transistor, particularly a bi-mode insulated gate transistor, is controlled by responding to an ON command by applying high-level gate voltage for a first period, during which a current is fed into a connection point, from which it flows either through the RC-IGBT or along a different path. Based hereon, it is determined whether the RC-IGBT conducts in its forward/IGBT or reverse/diode mode, and the RC-IGBT is either driven at high or low gate voltage. Subsequent conduction mode changes may be monitored in the same way, and the gate voltage may be adjusted accordingly. A special turn-off procedure may be applied in response to an OFF command in cases where the RC-IGBT conducts in the reverse mode, wherein a high-level pulse is applied for a second period before the gate voltage goes down to turn-off level.

公开(公告)号：US08749051B2

公开(公告)日：2014-06-10

申请号：US13367987

申请日：2012-02-07

Applicant: Slavo Kicin ,  Nicola Schulz ,  Munaf Rahimo ,  Raffael Schnell

Inventor： Slavo Kicin ,  Nicola Schulz ,  Munaf Rahimo ,  Raffael Schnell

IPC: H01L23/10

CPC classification number: H01L23/367 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/072 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device which provides a small and simple design with efficient cooling. A first electrically conducting cooling element is in contact with first electrodes of semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the first electrodes of the semiconductor elements to an external apparatus. A second electrically conducting cooling element is in contact with second electrodes of the semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the second electrodes of the semiconductor elements to an external apparatus. The semiconductor device includes an interface which is electrically connected to gates of the semiconductor elements for external control of respective states of the semiconductor elements.

Abstract translation: 一种半导体器件，提供小而简单的设计，有效的冷却。 第一导电冷却元件与半导体元件的第一电极接触，用于从半导体元件传递热负载并将半导体元件的第一电极电连接到外部设备。 第二导电冷却元件与半导体元件的第二电极接触，用于从半导体元件传送热负荷并将半导体元件的第二电极电连接到外部设备。 半导体器件包括电连接到半导体元件的栅极的接口，用于半导体元件的各自状态的外部控制。

公开(公告)号：US20120199954A1

公开(公告)日：2012-08-09

申请号：US13367987

申请日：2012-02-07

Applicant: Slavo KICIN ,  Nicola Schulz ,  Munaf Rahimo ,  Raffael Schnell

Inventor： Slavo KICIN ,  Nicola Schulz ,  Munaf Rahimo ,  Raffael Schnell

IPC: H01L29/02

CPC classification number: H01L23/367 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/072 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device which provides a small and simple design with efficient cooling. A first electrically conducting cooling element is in contact with first electrodes of semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the first electrodes of the semiconductor elements to an external apparatus. A second electrically conducting cooling element is in contact with second electrodes of the semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the second electrodes of the semiconductor elements to an external apparatus. The semiconductor device includes an interface which is electrically connected to gates of the semiconductor elements for external control of respective states of the semiconductor elements.

Abstract translation: 一种半导体器件，提供小而简单的设计，有效的冷却。 第一导电冷却元件与半导体元件的第一电极接触，用于从半导体元件传递热负载并将半导体元件的第一电极电连接到外部设备。 第二导电冷却元件与半导体元件的第二电极接触，用于从半导体元件传送热负荷并将半导体元件的第二电极电连接到外部设备。 半导体器件包括电连接到半导体元件的栅极的接口，用于半导体元件的各自状态的外部控制。

公开(公告)号：US20110136300A1

公开(公告)日：2011-06-09

申请号：US12951334

申请日：2010-11-22

Applicant: Jan VOBECKY ,  Munaf Rahimo

Inventor： Jan VOBECKY ,  Munaf Rahimo

IPC: H01L21/331

CPC classification number: H01L21/26513 ,  H01L21/268 ,  H01L29/0834 ,  H01L29/66333

Abstract: A method for producing a semiconductor device such as a RC-IGBT or a BIGT having a patterned surface wherein partial regions doped with dopants of a first conductivity type and regions doped with dopants of a second conductivity type are on a same side of a semiconductor substrate is proposed. An exemplary method includes: (a) implanting dopants of the first conductivity type and implanting dopants of the second conductivity type into the surface to be patterned; (b) locally activating dopants of the first conductivity type by locally heating the partial region of the surface to be patterned to a first temperature (e.g., between 900 and 1000° C.) using a laser beam similar to those used in laser annealing; and (c) activating the dopants of the second conductivity type by heating the substrate to a second temperature lower than the first temperature (e.g., to a temperature below 600° C.). Boron is an exemplary dopant of the first conductivity type, and phosphorous is an exemplary dopant of the second conductivity type. Boron can be activated in the regions irradiated only with the laser beam, whereas phosphorus may be activated in a low temperature sintering step on the entire surface.

Abstract translation: 一种用于制造具有图案化表面的诸如RC-IGBT或BIGT的半导体器件的方法，其中掺杂有第一导电类型的掺杂剂的部分区域和掺杂有第二导电类型的掺杂剂的区域在半导体衬底的同一侧 被提出。 一种示例性方法包括：（a）将第一导电类型的掺杂剂注入并将第二导电类型的掺杂剂注入到待图案化的表面中; （b）通过使用类似于激光退火中使用的激光束局部地将待图案化表面的部分区域加热到第一温度（例如在900和1000℃之间）来局部地激活第一导电类型的掺杂剂; 和（c）通过将衬底加热到​​低于第一温度的第二温度（例如，温度低于600℃）来激活第二导电类型的掺杂剂。 硼是第一导电类型的示例性掺杂剂，磷是第二导电类型的示例性掺杂剂。 可以在仅用激光束照射的区域中激活硼，而磷可以在整个表面上的低温烧结步骤中活化。

公开(公告)号：US20100276727A1

公开(公告)日：2010-11-04

申请号：US12770451

申请日：2010-04-29

Applicant: Liutauras STORASTA ,  Munaf Rahimo ,  Christoph Von Arx ,  Arnost Kopta ,  Raffael Schnell

Inventor： Liutauras STORASTA ,  Munaf Rahimo ,  Christoph Von Arx ,  Arnost Kopta ,  Raffael Schnell

IPC: H01L29/739

CPC classification number: H01L29/0834 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/7397

Abstract: A reverse-conducting semiconductor device is disclosed with an electrically active region, which includes a freewheeling diode and an insulated gate bipolar transistor on a common wafer. Part of the wafer forms a base layer with a base layer thickness. A first layer of a first conductivity type with at least one first region and a second layer of a second conductivity type with at least one second and third region are alternately arranged on the collector side. Each region has a region area with a region width surrounded by a region border. The RC-IGBT can be configured such that the following exemplary geometrical rules are fulfilled: each third region area is an area, in which any two first regions have a distance bigger (i.e., larger) than two times the base layer thickness; the at least one second region is that part of the second layer, which is not the at least one third region; the at least one third region is arranged in the central part of the active region in such a way that there is a minimum distance between the third region border to the active region border of at least once the base layer thickness; the sum of the areas of the at least one third region is between 10 and 30% of the active region; and each first region width is smaller than the base layer thickness.

Abstract translation: 公开了具有电活性区域的反向导电半导体器件，其包括在同一晶片上的续流二极管和绝缘栅双极晶体管。 晶片的一部分形成具有基层厚度的基底层。 具有至少一个第一区域和第二导电类型的具有至少一个第二和第三区域的第一导电类型的第一层交替地布置在集电极侧。 每个区域具有由区域边界包围的区域宽度的区域区域。 RC-IGBT可以被配置为使得满足以下示例性几何规则：每个第三区域区域是任何两个第一区域具有比基底层厚度的两倍大的距离（即，更大）的区域; 所述至少一个第二区域是所述第二层的不是所述至少一个第三区域的部分; 至少一个第三区域被布置在有源区域的中心部分中，使得在至少一次基底层厚度的第三区域边界与有源区域边界之间存在最小距离; 所述至少一个第三区域的面积之和为有效区域的10％至30％; 并且每个第一区域宽度小于基底层厚度。

公开(公告)号：US07446376B2

公开(公告)日：2008-11-04

申请号：US10579837

申请日：2004-11-16

Applicant: Munaf Rahimo ,  Stefan Linder

Inventor： Munaf Rahimo ,  Stefan Linder

IPC: H01L29/66

CPC classification number: B67D1/1422 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/7395

Abstract: In an insulated gate bipolar transistor, an improved safe operating area capability is achieved according to the invention by a two-fold base region comprising a first base region (81), which is disposed in the channel region (7) so that it encompasses the one or more source regions (6), but does not adjoin the second main surface underneath the gate oxide layer (41), and a second base region (82) is disposed in the semiconductor substrate (2) underneath the base contact area (821) so that it partially overlaps with the channel region (7) and with the first base region (81).

Abstract translation: 在绝缘栅双极晶体管中，根据本发明，通过包括设置在沟道区域（7）中的第一基极区域（81）的双折叠基极区域实现改进的安全工作面积能力，使得其包围 一个或多个源极区域（6），但不与栅极氧化物层（41）下面的第二主表面相邻，并且第二基极区域（82）设置在基极接触区域（821）下面的半导体衬底 ），使得其与沟道区域（7）和第一基极区域（81）部分重叠。

公开(公告)号：US07224008B2

公开(公告)日：2007-05-29

申请号：US10537834

申请日：2003-12-09

Applicant: Munaf Rahimo ,  Christoph Von Arx

Inventor： Munaf Rahimo ,  Christoph Von Arx

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L29/0696 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/423 ,  H01L29/4238 ,  H01L29/6634 ,  H01L29/7396

Abstract: The invention relates to a manufacturing method for an insulated gate semiconductor device cell, comprising the steps of forming a cell window (3) in a layered structure that is located on top of a semiconductor substrate (1), forming at least one process mask that partially covers the cell window (3). In forming the cell window (3), at least one strip (41, 42) of the layered structure is left to remain inside the cell window (3) and at least one strip (41, 42) is used to serve as an edge for the at least one process mask (51, 52).The invention further relates to an insulated gate semiconductor device, comprising a semiconductor substrate (1) having an essentially planar top surface and an insulated gate formed on the top surface by a layered structure (2) that comprises at least one electrically insulating layer (22), wherein at least one strip (41, 42) of the layered structure (2) is disposed on a third area of the top surface between an edge of the insulated gate and a first main contact (6).

Abstract translation: 本发明涉及一种用于绝缘栅半导体器件单元的制造方法，包括以下步骤：形成位于半导体衬底（1）顶部上的分层结构中的电池窗（3），形成至少一个工艺掩模， 部分地覆盖单元窗口（3）。 在形成电池窗（3）时，分层结构的至少一个条（41,42）留在电池窗（3）内，并且至少一个条（41,42）用作边缘 用于所述至少一个处理掩模（51,52）。 本发明还涉及一种绝缘栅极半导体器件，其包括具有基本上平坦的顶表面的半导体衬底（1）和通过层状结构（2）在顶表面上形成的绝缘栅极，所述层状结构（2）包括至少一个电绝缘层（22 ），其中所述层状结构（2）的至少一个条带（41,42）设置在所述绝缘栅极的边缘和第一主触头（6）之间的所述顶表面的第三区域上。

公开(公告)号：US08829571B2

公开(公告)日：2014-09-09

申请号：US13468593

申请日：2012-05-10

Applicant: Munaf Rahimo ,  Arnost Kopta ,  Jan Vobecky ,  Wolfgang Janisch

Inventor： Munaf Rahimo ,  Arnost Kopta ,  Jan Vobecky ,  Wolfgang Janisch

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/739

CPC classification number: H01L29/7395 ,  H01L29/0611 ,  H01L29/66333

Abstract: A maximum-punch-through semiconductor device such as an insulated gate bipolar transistor (IGBT) or a diode, and a method for producing same are disclosed. The MPT semiconductor device can include at least a two-layer structure having an emitter metallization, a channel region, a base layer with a predetermined doping concentration ND, a buffer layer and a collector metallization. A thickness W of the base layer can be determined by: W = V bd + V pt 4010 ⁢ ⁢ kV ⁢ ⁢ cm - 5 / 8 * ( N D ) 1 / 8 wherein a punch-through voltage Vpt of the semiconductor device is between 70% and 99% of a break down voltage Vbd of the semiconductor device, and wherein the thickness W is a minimum thickness of the base layer between a junction to the channel region and the buffer layer.

Abstract translation: 公开了诸如绝缘栅双极晶体管（IGBT）或二极管的最大穿通半导体器件及其制造方法。 MPT半导体器件可以包括具有发射极金属化的至少两层结构，沟道区，具有预定掺杂浓度ND的基极层，缓冲层和集电极金属化。 基底层的厚度W可以通过以下公式确定：W = V bd + V pt 4010注册kV电容cm -5 / 8 *（ND）1/8其中半导体器件的穿通电压Vpt在 70％和99％的半导体器件的击穿电压Vbd，并且其中厚度W是在结到通道区域与缓冲层之间的基底层的最小厚度。