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    Semiconductor integrated circuit and power supply control method therefor
    12.
    发明授权
    Semiconductor integrated circuit and power supply control method therefor 有权

    公开(公告)号：US09898070B2

    公开(公告)日：2018-02-20

    申请号：US14786453

    申请日：2014-01-07

    申请人： NEC CORPORATION

    发明人： Yukihide Tsuji ,  Noboru Sakimura ,  Ryusuke Nebashi ,  Ayuka Tada

    IPC分类号： G06F1/32 ,  G06F13/40

    CPC分类号： G06F1/3287 ,  G06F1/3209 ,  G06F1/3243 ,  G06F13/4022 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

    摘要： A semiconductor integrated circuit (100) comprising: a plurality of processing circuits (11, 12, 13) each including a notification units for outputting a notification signal according to the processing state of the own processing circuit; a plurality of power supply switch units (SW1, SW2, SW3) for switching the connection states between the respective processing circuits and a power supply source; a power supply switch control circuit which is connected with the notification means (111, 121, 131), stores power supply control information (101) including a plurality of connection statuses, and controls the connection states on the basis of the notification signals and the power supply control information; and a data bus (BS) and the like connecting each of the processing circuits and the power supply switch control circuit, wherein: at least two or more of the plurality of processing circuits update the power supply control information via the data bus and the like before outputting a notification signal; and the power supply switch control circuit accepts a notification signal outputted from any one of the plurality of processing circuits after the update, and accordingly controls the connection states of respective ones of the plurality of power supply switch units on the basis of the updated power supply control information.

    SEMICONDUCTOR DEVICE, POWER SUPPLY CONTROL METHOD OF SEMICONDUCTOR DEVICE, AND SENSOR NODE
    13.
    发明申请
    SEMICONDUCTOR DEVICE, POWER SUPPLY CONTROL METHOD OF SEMICONDUCTOR DEVICE, AND SENSOR NODE 有权
    半导体器件，半导体器件的电源控制方法和传感器节点

    公开(公告)号：US20150048680A1

    公开(公告)日：2015-02-19

    申请号：US14389311

    申请日：2013-03-28

    申请人： NEC CORPORATION

    发明人： Makoto Miyamura ,  Noboru Sakimura ,  Ryusuke Nebashi ,  Yukihide Tsuji ,  Tadahiko Sugibayashi

    IPC分类号： H02J1/08

    CPC分类号： H02J1/08 ,  H02J1/102 ,  Y10T307/406

    摘要： A semiconductor device includes a current control unit whose conductance is variable and a control unit configured to control the conductance of the current control unit. The current control unit is connected to a direct current power source in parallel with a load for the direct current power source, through a capacitor. The control unit sets the current control unit to a first conductance when the direct current power source and the load are not in a conduction state, and sets the current control unit to a second conductance larger than the first conductance when the direct current power source and the load are in the conduction state.

    摘要翻译： 半导体器件包括电导可变的电流控制单元和被配置为控制电流控制单元的电导的控制单元。 电流控制单元通过电容器与直流电源的负载并联连接到直流电源。 当直流电源和负载不处于导通状态时，控制单元将电流控制单元设置为第一电导，并且当直流电源和 负载处于导通状态。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD THEREFOR
    14.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD THEREFOR 审中-公开
    半导体集成电路及其控制方法

    公开(公告)号：US20140313843A1

    公开(公告)日：2014-10-23

    申请号：US14359879

    申请日：2012-11-20

    申请人： NEC Corporation

    发明人： Ryusuke Nebashi ,  Noboru Sakimura ,  Yukihide Tsuji ,  Ayuka Tada

    IPC分类号： G11C5/14

    CPC分类号： G11C5/148 ,  G06F1/24 ,  G06F1/3275 ,  G06F1/3287 ,  G06F11/1441 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C14/0081 ,  Y02D10/14 ,  Y02D10/171

    摘要： A semiconductor integrated circuit includes a plurality of first non-volatile registers including a retention circuit that retains volatile data and one or more non-volatile elements capable of retaining non-volatile data, and a second non-volatile register that retains a load enable bit that decides in which one of the plurality of first non-volatile registers data is loaded. The semiconductor integrated circuit also includes a non-volatile register control circuit that, when supply power is delivered from outside, loads to the retention circuit data retained by the non-volatile element(s) contained in the first non-volatile register specified by the load enable bit loaded from the second non-volatile register (FIG. 1).

    摘要翻译： 半导体集成电路包括多个第一非易失性寄存器，其包括保持易失性数据的保持电路和能够保存非易失性数据的一个或多个非易失性元件以及保持负载使能位的第二非易失性寄存器 决定多个第一非易失性寄存器数据中的哪一个被加载。 半导体集成电路还包括非易失性寄存器控制电路，当从外部传送电源时，将负载保存到由包含在由第一非易失性寄存器指定的第一非易失性寄存器中的非易失性元件所保留的保持电路数据 加载使能位从第二非易失性寄存器（图1）加载。

    Reconfigurable circuit and the method for using the same
    15.
    发明授权
    Reconfigurable circuit and the method for using the same 有权

    公开(公告)号：US11018671B2

    公开(公告)日：2021-05-25

    申请号：US16083965

    申请日：2017-04-06

    申请人： NEC Corporation

    发明人： Xu Bai ,  Toshitsugu Sakamoto ,  Yukihide Tsuji ,  Makoto Miyamura ,  Ayuka Tada ,  Ryusuke Nebashi

    IPC分类号： H03K19/177 ,  H03K19/17736 ,  H03K19/173 ,  H03K19/17704 ,  H03K19/17784 ,  H03K19/17796

    摘要： A reconfigurable circuit includes: a first line; a first switch element disposed between the first line and a first power source line of first voltage; a second line; a second switch element disposed between the second line and a second power source line of second voltage which is different from the first voltage; and a resistive switch assembly disposed between the first line and the second line. The resistive switch assembly includes: a first non-volatile resistive switch; and a second non-volatile resistive switch whose first end is coupled to a first end of the first non-volatile resistive switch. The second end of the first non-volatile resistive switch is coupled to the first line, and the second end of the second non-volatile resistive switch is coupled to the second line.

    Crossbar switch type memory circuit, look-up table circuit, and programming method
    17.
    发明授权
    Crossbar switch type memory circuit, look-up table circuit, and programming method 有权

    公开(公告)号：US10074421B2

    公开(公告)日：2018-09-11

    申请号：US15550463

    申请日：2016-03-01

    申请人： NEC Corporation

    发明人： Makoto Miyamura ,  Noboru Sakimura ,  Yukihide Tsuji ,  Ryusuke Nebashi ,  Tadahiko Sugibayashi

    IPC分类号： G11C11/00 ,  G11C13/00 ,  H01L27/24

    CPC分类号： G11C13/004 ,  G06F7/00 ,  G06F7/544 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0064 ,  G11C13/0069 ,  G11C29/12015 ,  G11C29/50008 ,  G11C29/52 ,  G11C2013/0073 ,  G11C2029/5004 ,  G11C2213/75 ,  H01L27/2445 ,  H01L27/2481

    摘要： In order to provide a crossbar switch type memory circuit designed to be usable in normal circumstances even when a resistance change element is in an adverse state, the present invention is provided with: a first unit including a first column wiring to which one end of a first resistance change element is connected, a first power supply-side transistor for controlling the connection of the first column wiring and a power supply node, a first ground-side transistor, of a reverse operation type to the first power supply-side transistor, for controlling the connection of the first column wiring and a ground node, and a first polarity control line for causing the first power supply-side transistor or the first ground-side transistor to turn on and the other to turn off by a polar signal from a polar signal terminal, the first polarity control line being connected to the control terminals of the first power supply-side transistor and first ground-side transistor; a second unit including a second column wiring to which one end of a second resistance change element is connected, a second power supply-side transistor, of the same operation type as the first power supply-side transistor, for controlling the connection of the second column wiring and the power supply node, a second ground-side transistor, of a reverse operation type to the second power supply-side transistor, for controlling the connection of the second column wiring and the ground node, a logic inversion circuit for inverting the polarity of the polar signal from the polar signal terminal and outputting the polarity-inverted signal, and a second polarity control line for causing the second power supply-side transistor or the second ground-side transistor to turn on and the other to turn off by a polar signal from the logic inversion circuit, the second polarity control line being connected to the control terminals of the second power supply-side transistor and second ground-side transistor; and n row wirings (n: positive integer) to which the other ends of the first and second resistance change elements are connected.