公开(公告)号：US20200145007A1

公开(公告)日：2020-05-07

申请号：US16621770

申请日：2017-08-10

Applicant: NEC Corporation

Inventor： Xu BAI ,  Toshitsugu SAKAMOTO ,  Yukihide TSUJI ,  Makoto MIYAMURA ,  Ayuka TADA ,  Ryusuke NEBASHI

IPC: H03K19/17736 ,  H03K19/173 ,  H03K19/17728

Abstract: A reconfigurable circuit comprising: crossbar switches; wires, each of which is coupled to one output port of one crossbar switch and input ports of the other crossbar switches; at least one inverter inserted on each wire for driving long-distance signal transfer, wherein one or less first inverter is inserted on the wire between two adjacent crossbar switches; one or two second inverters inserted between a crossbar switch input port and its connected wire.

公开(公告)号：US20190253057A1

公开(公告)日：2019-08-15

申请号：US16333317

申请日：2017-09-11

Applicant: NEC CORPORATION

Inventor： Xu BAI ,  Toshitsugu SAKAMOTO ,  Yukihide TSUJI ,  Ayuka TADA ,  Makoto MIYAMURA ,  Ryusuke NEBASHI

IPC: H03K19/177 ,  G11C13/00 ,  G06F17/50

Abstract: Provided is an integrated circuit that has reduced power consumption. The integrated circuit is provided with: a plurality of first wires one end of each of which is used as an input terminal; a plurality of second wires one end of each of which is used as an output terminal and which are respectively connected to the first wires; a bias wire which is connected to each of the second wires, and which is connected to a power supply or ground; a plurality of switches which connect the first wires or the bias wire and the second wires; and a selection circuit which selects electrical connection between the bias wire and the power supply or ground.

公开(公告)号：US20180302094A1

公开(公告)日：2018-10-18

申请号：US15767683

申请日：2015-10-16

Applicant: NEC Corporation

Inventor： Xu BAI ,  Toshitsugu SAKAMOTO ,  Munehiro TADA ,  Yukihide TSUJI ,  Ayuka TADA ,  Makoto MIYAMURA ,  Ryusuke NEBASHI

IPC: H03K19/177 ,  G06F17/50 ,  G06F15/78

CPC classification number: H03K19/17756 ,  G06F15/7867 ,  G06F17/5054 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1776

Abstract: A reconfigurable circuit includes first and second wires and two or more paths active at different times. Each path includes: a first NVRS whose first terminal is connected to the first wire; a first transistor whose drain terminal is connected to a second terminal of the first NVRS; a second NVRS whose first terminal is connected to the second terminal of the first NVRS; a second transistor whose source terminal is connected to a second terminal of the second NVRS and whose drain terminal is connected to the second wire; and a 2-input AND circuit whose output is connected to a gate terminal of the first transistor. A time control signal is supplied to a first input of the 2-input AND circuit and a gate terminal of the second transistor. A write control signal is supplied to a second input of the 2-input AND circuit.

公开(公告)号：US20210133379A1

公开(公告)日：2021-05-06

申请号：US16478517

申请日：2018-01-22

Applicant: NEC Corporation

Inventor： Ryusuke NEBASHI ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Yukihide TSUJI ,  Ayuka TADA ,  Xu BAI

IPC: G06F30/31 ,  G06F30/394

Abstract: A design assistance system according to the present invention assists in designing a circuit to be mounted on a programmable logic integrated circuit including a resistance change element. The design assistance system includes: a memory; and at least one processor coupled to the memory. The processor performs operations. The operations includes: generating rewriting history information indicating a number (count) of changing times of a state of the resistance change element; calculating an abrasion cost of a switch included in the circuit, based on the rewriting history information; and carrying out wiring of the circuit, based on an evaluation function including the abrasion cost.

公开(公告)号：US20200381045A1

公开(公告)日：2020-12-03

申请号：US16970495

申请日：2019-03-12

Applicant: NEC Corporation

Inventor： Toshitsugu SAKAMOTO ,  Ryusuke NEBASHI ,  Makoto MIYAMURA ,  Xu BAI ,  Yukihide TSUJI

IPC: G11C13/00 ,  H03K19/177 ,  H01L27/24 ,  H01L45/00

Abstract: A semiconductor device which includes: a switch array in which a switch cell including a variable resistance switch is arranged at each location where a plurality of wires constituting a crossbar switch intersect; a first selection circuit that selects all of the variable resistance switches included in the switch array; a second selection circuit that selects any of the variable resistance switches included in the switch array; a reading circuit that reads a state of the variable resistance switch selected by any of the first selection circuit and the second selection circuit; and an error detection circuit that detects, based on a state of the variable resistance switch read by the reading circuit, an error in at least any of the variable resistance switches included in the switch array.

公开(公告)号：US20200350909A1

公开(公告)日：2020-11-05

申请号：US16964392

申请日：2019-02-08

Applicant: NEC Corporation

Inventor： Makoto MIYAMURA ,  Ryusuke NEBASHI ,  Toshitsugu SAKAMOTO ,  Yukihide TSUJI ,  Xu BAI ,  Ayuka TADA

IPC: H03K17/693 ,  G11C13/00

Abstract: A semiconductor device includes: first wires which extend in a first direction; second wires extending in a second direction; a unit element which comprises two variable resistance elements connected in series, and has one end connected to a first wire and the other end connected to a second wire; a first control line for controlling the supply of a voltage to the first wire; a second control line for controlling the supply of a voltage to the second wire; and a cell circuit connected to an intermediate node between the two variable resistance elements and also connected to the first control line and the second control line. The cell circuit has: a cell transistor connected to an intermediate node writing driver which supplies a voltage to the intermediate node; and a cell control circuit which controls an electrical conduction state of the cell transistor.

公开(公告)号：US20200251496A1

公开(公告)日：2020-08-06

申请号：US16648757

申请日：2018-09-14

Applicant: NEC Corporation

Inventor： Makoto MIYAMURA ,  Toshitsugu SAKAMOTO ,  Yukihide TSUJI ,  Ryusuke NEBASHI ,  Ayuka TADA ,  Xu BAI

IPC: H01L27/118 ,  G11C11/56 ,  G11C13/00 ,  G06F30/327

Abstract: A programmable integrated circuit includes: a crossbar switch constituted of a plurality of first wires arranged in a first direction, a plurality of second wires arranged in a second direction intersecting the first direction, and resistance change type elements connecting the first wires and the second wires; an output buffer group constituted of at least two output buffers operating with different drive powers; and a logic circuit group constituted of at least one logic circuit connected to an output of the second wire. The output buffers in the output buffer group is connected to an input of any one of a plurality of the first wires.

公开(公告)号：US20200234760A1

公开(公告)日：2020-07-23

申请号：US16489912

申请日：2018-02-28

Applicant: NEC CORPORATION

Inventor： Makoto MIYAMURA ,  Yukihide TSUJI ,  Toshitsugu SAKAMOTO ,  Ryusuke NEBASHI ,  Ayuka TADA ,  Xu BAI

IPC: G11C13/00

Abstract: In order to eliminate an increase in the source potential of a transistor selected during writing or reading, this semiconductor device is equipped with: a variable-resistance type first switch having a first terminal and a second terminal; a variable-resistance type second switch having a third terminal and a fourth terminal, the third terminal being connected to the second terminal to form an intermediate node; first wiring connected to the first terminal; second wiring connected to the fourth terminal and, in a planar view, extending in a direction crossing the first wiring; a first selection transistor connected to the first wiring; a second selection transistor connected to the second wiring; a first well terminal connection line to which a well terminal of the first selection transistor is connected; and a second well terminal connection line to which a well terminal of the second selection transistor is connected.

公开(公告)号：US20190028101A1

公开(公告)日：2019-01-24

申请号：US16061701

申请日：2017-01-16

Applicant: NEC Corporation

Inventor： Ryusuke NEBASHI ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Yukihide TSUJI ,  Ayuka TADA ,  Xu BAI

IPC: H03K19/003 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00 ,  G06F11/07

Abstract: An object of the present invention is to provide a logic integrated circuit that increases reliability of configuration information held in a switch while maintaining high tamper resistance and a small chip area. The logic integrated circuit according to the present invention includes: a three-terminal resistance change switch including a first resistance change switch and a second resistance change switch connected in series; a reading circuit which reads first data based on a resistance state of the first resistance change switch and second data based on a resistance state of the second resistance change switch; and a first error detection circuit which compares the first data with the second data and issue an output based on a result of the comparison.

公开(公告)号：US20170256587A1

公开(公告)日：2017-09-07

申请号：US15508980

申请日：2015-09-11

Applicant: NEC Corporation

Inventor： Yukihide TSUJI ,  Xu BAI ,  Makoto MIYAMURA ,  Toshitsugu SAKAMOTO ,  Munehiro TADA

IPC: H01L27/24 ,  H03K19/177 ,  H01L23/522 ,  H03K19/173 ,  H01L45/00 ,  H01L23/528

Abstract: A purpose of the invention is to provide a crossbar switch for reducing the layout areas of a crossbar switch and peripheral circuits thereof. A crossbar switch of the invention comprises: a plurality of first wires extending in a first direction; a plurality of second wires extending in a second direction; a plurality of third wires extending in a third direction; a plurality of fourth wires extending in a fourth direction; and a plurality of switch cells connected to the first and second wires. The first wires are skew relative to the second and fourth wires, while the third wires are skew relative to the second and fourth wires. The switch cells are connected to the third and fourth wires, and further, the third wires are also connected to the switch cells connected to the first wires adjacent to the respective first wires; or alternatively, further, the fourth wires are also connected to the switch cells connected to the second wires adjacent to the respective second wires.