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    LOGIC INTEGRATED CIRCUIT
    1.
    发明申请
    LOGIC INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20200266822A1

    公开(公告)日：2020-08-20

    申请号：US16648820

    申请日：2018-09-14

    Applicant: NEC Corporation

    Inventor： Yukihide TSUJI ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Ryusuke NEBASHI ,  Ayuka TADA ,  Xu BAI

    IPC: H03K19/185 ,  H03K19/173 ,  H03K19/17704 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00 ,  H03K19/17728 ,  H03K19/17756 ,  G06F7/57

    Abstract: This logic integrated circuit has a plurality of first switch cells including variable resistance elements and a plurality of second switch cells including variable resistance elements. The logic integrated circuit comprises: a first output port and a second output port; the plurality of first switch cells for switching the electrical connections between a first wire and a third wire; the plurality of second switch cells for switching the electrical connections between a second wire and the third wire; a first control transistor which is connected to the first wire and which is for switching the electrical connections between the first wire and a first power line supplying power to the first wire; and a second control transistor which is connected to the second wire and which is for switching the electrical connections between the second wire and the first power line supplying power to the second wire.

    RECONFIGURABLE CIRCUIT AND THE METHOD FOR USING THE SAME
    4.
    发明申请
    RECONFIGURABLE CIRCUIT AND THE METHOD FOR USING THE SAME 审中-公开

    公开(公告)号：US20200295761A1

    公开(公告)日：2020-09-17

    申请号：US16083978

    申请日：2016-05-13

    Applicant: NEC Corporation

    Inventor： Xu BAI ,  Toshitsugu SAKAMOTO ,  Yukihide TSUJI ,  Makoto MIYAMURA ,  Ayuka TADA ,  Ryusuke NEBASHI

    IPC: H03K19/177

    Abstract: A reconfigurable circuit comprising: a first line; a first switch element disposed between the first line and a first power source line of first voltage; a second line; a second switch element disposed between the second line and a second power source line of second voltage which is different from the first voltage; and a resistive switch assembly disposed between the first line and the second line. The resistive switch assembly including a first non-volatile resistive switch, and a second non-volatile resistive switch whose first end is coupled to a first end of the first non-volatile resistive switch. The second end of the first non-volatile resistive switch is coupled to the first line, and the second end of the second non-volatile resistive switch is coupled to the second line.

    RECONFIGURABLE CIRCUIT
    6.
    发明申请
    RECONFIGURABLE CIRCUIT 有权

    公开(公告)号：US20170331480A1

    公开(公告)日：2017-11-16

    申请号：US15531816

    申请日：2015-01-21

    Applicant: NEC CORPORATION

    Inventor： Xu BAI ,  Yukihide TSUJI

    IPC: H03K19/094 ,  H03K19/177 ,  H03K19/173 ,  H01L27/24

    CPC classification number: H03K19/09429 ,  H01L27/2436 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17744 ,  H03K19/17748

    Abstract: The invention is to provide a compact reconfigurable circuit implementing a LUT and a “hard” circuit. The present invention provides a reconfigurable circuit comprising: first wires disposed in a first direction; a second wire disposed in a second direction intersecting the first direction; a power line, a ground line and data input line or data input inverse line coupled to the said first wires one-to-one; a multiplexer, one of whose inputs is connected with the second wire; nonvolatile switch cells utilized to interconnect the first wires and second wire at the crosspoints, wherein every nonvolatile switch cell is constructed by at least one non-volatile resistive switch.

    DESIGN ASSISTANCE SYSTEM, DESIGN ASSISTANCE METHOD, AND PROGRAM RECORDING MEDIUM
    8.
    发明申请
    DESIGN ASSISTANCE SYSTEM, DESIGN ASSISTANCE METHOD, AND PROGRAM RECORDING MEDIUM 审中-公开

    公开(公告)号：US20200380190A1

    公开(公告)日：2020-12-03

    申请号：US16766467

    申请日：2018-11-21

    Applicant: NEC Corporation

    Inventor： Ryusuke NEBASHI ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Yukihide TSUJI ,  Ayuka TADA ,  Xu BAI

    IPC: G06F30/343 ,  G06F30/347

    Abstract: A design assistance system including: a logic synthesis unit that receives input of an operation description file of the programmable logic integrated circuit, logically synthesizes the inputted operation description file, and generates a net list by using logic elements included in the programmable logic integrated circuit; an arrangement wiring unit that generates resource information of the programmable logic integrated circuit, arranges the logic elements included in the net list on the basis of the generated resource information, and virtually generates a signal path by laying wires among the arranged logic elements; and a reliability control unit that generates configuration information of the programmable logic integrated circuit on the basis of at least two reliability modes, and outputs the generated configuration information.

    LOGIC INTEGRATED CIRCUIT
    9.
    发明申请
    LOGIC INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20200336145A1

    公开(公告)日：2020-10-22

    申请号：US16957973

    申请日：2019-01-21

    Applicant: NEC Corporation

    Inventor： Ryusuke NEBASHI ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Yukihide TSUJI ,  Ayuka TADA ,  Xu BAI

    IPC: H03K19/17736 ,  H03K19/17704 ,  H03K19/1776 ,  G11C13/00

    Abstract: A logic integrated circuit includes a switch cell array. The switch cell array includes: a plurality of first wirings extending in a first direction; a plurality of second wirings extending in a second direction; a switch cell including a unit element including two serially connected resistance-changing elements, and a cell transistor to be connected to a shared terminal of the two resistance-changing elements; and a bit line to which the shared terminal is connected via the cell transistor. Two of the switch cells adjacent to each other in the first direction are each connected to the different first wiring and second wiring, and share the bit line, and a diffusion layer to which the bit line is connected.

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