公开(公告)号：US20200295761A1

公开(公告)日：2020-09-17

申请号：US16083978

申请日：2016-05-13

Applicant: NEC Corporation

Inventor： Xu BAI ,  Toshitsugu SAKAMOTO ,  Yukihide TSUJI ,  Makoto MIYAMURA ,  Ayuka TADA ,  Ryusuke NEBASHI

IPC: H03K19/177

Abstract: A reconfigurable circuit comprising: a first line; a first switch element disposed between the first line and a first power source line of first voltage; a second line; a second switch element disposed between the second line and a second power source line of second voltage which is different from the first voltage; and a resistive switch assembly disposed between the first line and the second line. The resistive switch assembly including a first non-volatile resistive switch, and a second non-volatile resistive switch whose first end is coupled to a first end of the first non-volatile resistive switch. The second end of the first non-volatile resistive switch is coupled to the first line, and the second end of the second non-volatile resistive switch is coupled to the second line.

公开(公告)号：US20180123595A1

公开(公告)日：2018-05-03

申请号：US15572653

申请日：2015-05-28

Applicant: NEC Corporation

Inventor： Xu BAI ,  Noboru SAKIMURA ,  Yukihide TSUJI ,  Ryusuke NEBASHI ,  Ayuka TADA ,  Makoto MIYAMURA

IPC: H03K19/177

CPC classification number: H03K19/17728 ,  G11C7/06 ,  G11C7/1051 ,  G11C7/1078 ,  H03K19/1736 ,  H03K19/17744

Abstract: A reconfigurable circuit comprising: a first level crossbar switch that has first non-volatile resistive switches; a second level crossbar switch that has second non-volatile resistive switches; and a first wire and third non-volatile resistive switches that are used for redundancy, wherein input wires of the second level crossbar switch are connected to output wires of the first level crossbar switch one-to-one, and input wires of the first level crossbar switch and output wires of the second level crossbar switch are connected to the first wire through the third non-volatile resistive switches.

公开(公告)号：US20170331480A1

公开(公告)日：2017-11-16

申请号：US15531816

申请日：2015-01-21

Applicant: NEC CORPORATION

Inventor： Xu BAI ,  Yukihide TSUJI

IPC: H03K19/094 ,  H03K19/177 ,  H03K19/173 ,  H01L27/24

CPC classification number: H03K19/09429 ,  H01L27/2436 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17744 ,  H03K19/17748

Abstract: The invention is to provide a compact reconfigurable circuit implementing a LUT and a “hard” circuit. The present invention provides a reconfigurable circuit comprising: first wires disposed in a first direction; a second wire disposed in a second direction intersecting the first direction; a power line, a ground line and data input line or data input inverse line coupled to the said first wires one-to-one; a multiplexer, one of whose inputs is connected with the second wire; nonvolatile switch cells utilized to interconnect the first wires and second wire at the crosspoints, wherein every nonvolatile switch cell is constructed by at least one non-volatile resistive switch.

公开(公告)号：US20170070228A1

公开(公告)日：2017-03-09

申请号：US15122433

申请日：2015-02-27

Applicant: NEC Corporation

Inventor： Ryusuke NEBASHI ,  Makoto MIYAMURA ,  Noboru SAKIMURA ,  Yukihide TSUJI ,  Ayuka TADA

IPC: H03K19/177 ,  G11C29/00 ,  H03K19/173

CPC classification number: H03K19/17736 ,  G11C29/86 ,  H03K19/1736 ,  H03K19/1776

Abstract: In a programmable logic integrated circuit, providing a spare circuit in preparation for the occurrence of a defective element results in a redundant circuit configuration. A programmable logic integrated circuit according to the present invention has: a plurality of logic blocks; a switch block for switching the connections between row and column wires by nonvolatile switch elements for switching; and a shifter block for connecting an input/output wire to said switch block. The shifter block includes a redundant wire and is equipped with nonvolatile switch elements for shifting that control the connections of the wires constituting said redundant wire and said row wires.

Abstract translation: 在可编程逻辑集成电路中，提供备用电路以准备故障元件的出现导致冗余电路配置。 根据本发明的可编程逻辑集成电路具有：多个逻辑块; 用于通过用于切换的非易失性开关元件来切换行和列线之间的连接的开关块; 以及用于将输入/输出线连接到所述开关块的移位块。 移位器块包括冗余线，并且配备有用于移位的非易失性开关元件，用于控制构成所述冗余线和所述行线的线的连接。

公开(公告)号：US20160274804A1

公开(公告)日：2016-09-22

申请号：US14777690

申请日：2014-03-24

Applicant: NEC CORPORATION

Inventor： Yukihide TSUJI ,  Yukikazu NAKAMOTO

IPC: G06F3/06 ,  G06F1/32

CPC classification number: G06F3/0619 ,  G06F1/24 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3287 ,  G06F3/0625 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0685 ,  G06F9/4401 ,  G06F11/1441 ,  Y02B70/12 ,  Y02B70/32 ,  Y02D10/171 ,  Y02D50/20

Abstract: In order to ensure that a normally-off computer connected to a volatile component operates normally and rapidly after operation of turning-on/off of a power supply is executed, a computation processing device which has nonvolatile registers and which is able to continue processing of data retained in the device after the power supply is turned off/on without retracting the data to an external device includes at least: a central processing unit including the nonvolatile registers; a connection unit for a volatile component which saves internal information in a volatile storage element thereof; a nonvolatile storage unit for saving a return program from a power-off state of the volatile component; and an inspection unit notifying that a potential of the power supply in the computation processing device has reached an operation potential at a time of return. The central processing unit loads the return program from the nonvolatile storage unit in response to a notification signal from the inspection unit and executes it.

Abstract translation: 为了确保连接到易失性组件的常闭计算机在执行电源的接通/断开之后正常且快速地运行，具有非易失性寄存器并且能够继续处理的计算处理装置 在电源关闭/接通之后保留在设备中的数据不会将数据缩回到外部设备至少包括：包括非易失性寄存器的中央处理单元; 用于将内部信息保存在其易失性存储元件中的用于易失性组件的连接单元; 非易失性存储单元，用于从所述易失性组件的关闭状态保存返回程序; 以及检查单元，其通知计算处理装置中的电源的电位在返回时已经达到操作电位。 中央处理单元响应于来自检查单元的通知信号而从非易失性存储单元加载返回程序并执行它。

公开(公告)号：US20160077563A1

公开(公告)日：2016-03-17

申请号：US14786453

申请日：2014-01-07

Applicant: NEC CORPORATION

Inventor： Yukihide TSUJI ,  Noboru SAKIMURA ,  Ryusuke NEBASHI ,  Ayuka TADA

IPC: G06F1/26 ,  G06F13/40

CPC classification number: G06F1/3287 ,  G06F1/3209 ,  G06F1/3243 ,  G06F13/4022 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

Abstract: A semiconductor integrated circuit (100) comprising: a plurality of processing circuits (11, 12, 13) each including a notification units for outputting a notification signal according to the processing state of the own processing circuit; a plurality of power supply switch units (SW1, SW2, SW3) for switching the connection states between the respective processing circuits and a power supply source; a power supply switch control circuit which is connected with the notification means (111, 121, 131), stores power supply control information (101) including a plurality of connection statuses, and controls the connection states on the basis of the notification signals and the power supply control information; and a data bus (BS) and the like connecting each of the processing circuits and the power supply switch control circuit, wherein: at least two or more of the plurality of processing circuits update the power supply control information via the data bus and the like before outputting a notification signal; and the power supply switch control circuit accepts a notification signal outputted from any one of the plurality of processing circuits after the update, and accordingly controls the connection states of respective ones of the plurality of power supply switch units on the basis of the updated power supply control information.

Abstract translation: 一种半导体集成电路（100），包括：多个处理电路（11,12,13），每个处理电路包括根据本处理电路的处理状态输出通知信号的通知单元; 用于切换各个处理电路和电源之间的连接状态的多个电源开关单元（SW1，SW2，SW3） 与通知装置（111,121,131）连接的电源开关控制电路存储包括多个连接状态的电源控制信息（101），并且基于通知信号来控制连接状态， 电源控制信息; 以及连接处理电路和电源开关控制电路中的每一个的数据总线（BS）等，其中：多个处理电路中的至少两个或更多个通过数据总线等来更新电源控制信息 在输出通知信号之前; 并且电源开关控制电路接受在更新之后从多个处理电路中的任一个输出的通知信号，并且因此基于更新的电源来控制多个电源开关单元中的各个电源开关单元的连接状态 控制信息。

公开(公告)号：US20210020238A1

公开(公告)日：2021-01-21

申请号：US16980211

申请日：2018-03-23

Applicant: NEC Corporation

Inventor： Xu BAI ,  Toshitsugu SAKAMOTO ,  Yukihide TSUJI ,  Makoto MIYAMURA ,  Ryusuke NEBASHI ,  Ayuka TADA

IPC: G11C13/00 ,  H03M5/02 ,  H03K19/1776

Abstract: A reconfigurable circuit includes: a complementary resistive switch including a first resistive switch, a second resistive switch and a selection transistor, wherein a first terminal of the first resistive switch is connected to a first terminal of the second resistive switch and connected to a first terminal of the selection transistor; a first current source having a first terminal connected to a second terminal of the first resistive switch and a second terminal connected to a ground voltage line; a second current source having a first terminal connected to a second terminal of the second resistive switch and a second terminal connected to the ground voltage line; and a resistor having a first terminal connected to a second terminal of the selection transistor and a second terminal connected to a power voltage line.

公开(公告)号：US20200295764A1

公开(公告)日：2020-09-17

申请号：US16083965

申请日：2017-04-06

Applicant: NEC Corporation

Inventor： Xu BAI ,  Toshitsugu SAKAMOTO ,  Yukihide TSUJI ,  Makoto MIYAMURA ,  Ayuka TADA ,  Ryusuke NEBASHI

IPC: H03K19/17736 ,  H03K19/17796 ,  H03K19/17704 ,  H03K19/17784 ,  H03K19/173

Abstract: A reconfigurable circuit includes: a first line; a first switch element disposed between the first line and a first power source line of first voltage; a second line; a second switch element disposed between the second line and a second power source line of second voltage which is different from the first voltage; and a resistive switch assembly disposed between the first line and the second line. The resistive switch assembly includes: a first non-volatile resistive switch; and a second non-volatile resistive switch whose first end is coupled to a first end of the first non-volatile resistive switch. The second end of the first non-volatile resistive switch is coupled to the first line, and the second end of the second non-volatile resistive switch is coupled to the second line.

公开(公告)号：US20190180818A1

公开(公告)日：2019-06-13

申请号：US16324782

申请日：2017-09-11

Applicant: NEC Corporation

Inventor： Makoto MIYAMURA ,  Ryusuke NEBASHI ,  Toshitsugu SAKAMOTO ,  Yukihide TSUJI ,  Xu BAI ,  Ayuka TADA

IPC: G11C13/00

Abstract: In order to provide a highly reliable crossbar circuit that enables salvation of reversal of a resistive state of a variable resistance element, the semiconductor device has a configuration obtained by parallelly arranging two unit elements, each including variable-resistance two-terminal elements connected in series, the semiconductor device being provided with: a unit element group being connected to a first wiring and a second wiring; a first programming driver that changes, via the first wiring, a resistive state of the two-terminal element constituting the unit element group; a first selection transistor being connected to the first wiring and the first programming driver; a second programming driver that changes, via the second wiring, a resistive state of the two-terminal element constituting the unit element group; and a second selection transistor being connected to the second wiring and the second programming driver.

公开(公告)号：US20190052273A1

公开(公告)日：2019-02-14

申请号：US15752330

申请日：2016-08-31

Applicant: NEC Corporation

Inventor： Ayuka TADA ,  Noboru SAKIMURA ,  Makoto MIYAMURA ,  Yukihide TSUJI ,  Ryusuke NEBASHI ,  Xu BAI ,  Toshitsugu SAKAMOTO

IPC: H03K19/177 ,  G06F17/50 ,  H01L27/24 ,  H01L45/00

Abstract: An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.