公开(公告)号：US20140189329A1

公开(公告)日：2014-07-03

申请号：US13728784

申请日：2012-12-27

Applicant: NVIDIA CORPORATION

Inventor： Gerald F. LUIZ ,  Philip Alexander CUADRA ,  Luke DURANT ,  Shirish GADRE ,  Robert OHANNESSIAN ,  Lacky V. SHAH ,  Nicholas WANG ,  Arthur DANSKIN

IPC: G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/3861 ,  G06F9/3887 ,  G06F9/4812

Abstract: Techniques are provided for handling a trap encountered in a thread that is part of a thread array that is being executed in a plurality of execution units. In these techniques, a data structure with an identifier associated with the thread is updated to indicate that the trap occurred during the execution of the thread array. Also in these techniques, the execution units execute a trap handling routine that includes a context switch. The execution units perform this context switch for at least one of the execution units as part of the trap handling routine while allowing the remaining execution units to exit the trap handling routine before the context switch. One advantage of the disclosed techniques is that the trap handling routine operates efficiently in parallel processors.

Abstract translation: 提供了用于处理在作为在多个执行单元中执行的线程数组的一部分的线程中遇到的陷阱的技术。 在这些技术中，具有与线程相关联的标识符的数据结构被更新，以指示在执行线程数组期间发生陷阱。 同样在这些技术中，执行单元执行包括上下文切换的陷阱处理例程。 执行单元为至少一个执行单元执行该上下文切换，作为陷阱处理例程的一部分，同时允许剩余执行单元在上下文切换之前退出陷阱处理例程。 所公开技术的一个优点是陷阱处理例程在并行处理器中有效地操作。

公开(公告)号：US20140189260A1

公开(公告)日：2014-07-03

申请号：US13728813

申请日：2012-12-27

Applicant: NVIDIA CORPORATION

Inventor： Nicholas WANG ,  Shirish GADRE ,  Robert OHANNESSIAN ,  Lacky V. SHAH ,  Matthew BROCKMEYER ,  Stewart Glenn CARLTON

IPC: G06F12/14

CPC classification number: G06F12/1416 ,  G06F9/46 ,  G06F9/52 ,  G06F12/1466 ,  G06F17/30171

Abstract: A streaming multiprocessor in a parallel processing subsystem processes atomic operations for multiple threads in a multi-threaded architecture. The streaming multiprocessor receives a request from a thread in a thread group to acquire access to a memory location in a lock-protected shared memory, and determines whether a address lock in a plurality of address locks is asserted, where the address lock is associated the memory location. If the address lock is asserted, then the streaming multiprocessor refuses the request. Otherwise, the streaming multiprocessor asserts the address lock, asserts a thread group lock in a plurality of thread group locks, where the thread group lock is associated with the thread group, and grants the request. One advantage of the disclosed techniques is that acquired locks are released when a thread is preempted. As a result, a preempted thread that has previously acquired a lock does not retain the lock indefinitely.

Abstract translation: 并行处理子系统中的多流处理器在多线程架构中处理多个线程的原子操作。 流式多处理器从线程组中的线程接收请求以获得对锁定保护的共享存储器中的存储器位置的访问，并且确定多个地址锁中的地址锁定是否被断言，其中地址锁定与 内存位置。 如果地址锁定被确认，则流式多处理器拒绝该请求。 否则，流多处理器断言地址锁定，在多个线程组锁定中断定线程组锁定，其中线程组锁与线程组相关联，并且授予该请求。 所公开技术的一个优点是当线程被抢占时获得的锁定被释放。 因此，先前获得锁定的抢占线程不会无限期地保留锁定。

公开(公告)号：US20140184617A1

公开(公告)日：2014-07-03

申请号：US13728881

申请日：2012-12-27

Applicant: NVIDIA CORPORATION

Inventor： Gregory Scott PALMER ,  Ziyad S. HAKURA ,  Emmett M. KILGARIFF ,  Dale L. KIRKLAND ,  Lacky V. SHAH

IPC: G06F9/38

CPC classification number: G06T1/20

Abstract: One embodiment of the present invention sets forth a technique for mid-primitive execution preemption. When preemption is initiated no new instructions are issued, in-flight instructions progress to an execution unit boundary, and the execution state is unloaded from the processing pipeline. The execution units within the processing pipeline, including the coarse rasterization unit complete execution of in-flight instructions and become idle. However, rasterization of a triangle may be preempted at a coarse raster region boundary. The amount of context state to be stored is reduced because the execution units are idle. Preempting at the mid-primitive level during rasterization reduces the time from when preemption is initiated to when another process can execute because the entire triangle is not rasterized.

Abstract translation: 本发明的一个实施例提出了一种用于中原始执行抢占的技术。 当启动抢占时，不会发出新的指令，飞行中的指令进行到执行单位边界，执行状态从处理流水线中卸载。 处理流水线内的执行单元，包括粗略光栅化单元，完成飞行中指令的执行并变为空闲状态。 然而，在粗略的栅格区域边界处，可以抢占三角形的光栅化。 由于执行单元是空闲的，因此减少了要存储的上下文状态量。 在光栅化过程中，在中等原始级别抢占时间减少了从抢占启动到另一个进程可以执行的时间，因为整个三角形不被光栅化。

公开(公告)号：US20140173258A1

公开(公告)日：2014-06-19

申请号：US13720746

申请日：2012-12-19

Applicant: NVIDIA CORPORATION

Inventor： Brian FAHS ,  Eric T. ANDERSON ,  Nick BARROW-WILLIAMS ,  Shirish GADRE ,  Joel James MCCORMACK ,  Bryon S. NORDQUIST ,  Nirmal Raj SAXENA ,  Lacky V. SHAH

IPC: G06F9/30

CPC classification number: G06F9/3887 ,  G06F9/3851 ,  G06F12/0284 ,  G06F12/0815 ,  G06F12/0844 ,  G06F2209/5018 ,  G06F2212/604

Abstract: A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture processing pipeline may retrieve texture data based on texture coordinates. When the memory access request represents a generic data access operation, the texture pipeline extracts a virtual address from the memory access request and then retrieves data based on the virtual address. The texture processing pipeline is also configured to cache generic data retrieved on behalf of a group of threads and to then invalidate that generic data when the group of threads exits.

Abstract translation: 可以将纹理处理流水线配置为服务于表示纹理数据访问操作或通用数据访问操作的存储器访问请求。 当纹理处理流水线接收到表示纹理数据访问操作的存储器访问请求时，纹理处理流水线可以基于纹理坐标来检索纹理数据。 当存储器访问请求表示通用数据访问操作时，纹理流水线从存储器访问请求中提取虚拟地址，然后基于虚拟地址检索数据。 纹理处理流水线还被配置为缓存代表一组线程检索的通用数据，然后在线程组退出时使该通用数据无效。