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公开(公告)号：US11038522B1
公开(公告)日：2021-06-15
申请号：US16779976
申请日：2020-02-03
Applicant: NXP B.V.
Inventor： Johan Frederik Witte , Lucien Johannes Breems , Robert Rutten , Muhammed Bolatkale , Johannes Hubertus Antonius Brekelmans , Shagun Bajoria , Albertus Willibrordus Oude Essink
Abstract: An apparatus including analog-to-digital conversion (ADC) circuitry is disclosed. The apparatus includes a plurality of comparators susceptible to offset variation and a shuffler circuit configured to shuffle input sources to the respective comparators. Feedback circuitry is also included and is configured and arranged with the ADC circuitry to detect offset variation in the outputs of each comparators for the shuffled inputs, relative to outputs of the plurality of comparators and compensate for the offset variation in the comparators based on the offset differences between the respective comparators.
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公开(公告)号：US20200076671A1
公开(公告)日：2020-03-05
申请号：US16122132
申请日：2018-09-05
Applicant: NXP B.V.
Inventor： Juergen Richard Marschner , Robert Rutten , Niels Gabriel , Tjeu van Ansem , Francoise Jeannette Harmsze , Peter Blinzer , Frits Anthonie Steenhof
Abstract: Certain aspects of the disclosure are directed to in-phase/quadrature (IQ) mismatch detection and correction in radio frequency receivers. According to a specific example, a method of manufacture or use comprises, in a quadrature radio-frequency receiver configured to process signals using I and Q components, providing parameters indicative of IQ mismatches associated with circuitry of the quadrature radio-frequency receiver due to changes in signal gain. The method further includes, while using the quadrature radio-frequency receiver to receive and process a received radio signal, correcting for the IQ mismatches by using the parameters in response to actual signal gain change.
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公开(公告)号：US10098146B2
公开(公告)日：2018-10-09
申请号：US15356451
申请日：2016-11-18
Applicant: NXP B.V.
Inventor： Jan Niehof , Shagun Bajoria , Muhammed Bolatkale , Robert Rutten , Lucien Johannes Breems , Johannes Hubertus Antonius Brekelmans
Abstract: A processor is disclosed. The processor includes a first-receiver-node for receiving a first-receiver-signal, a second-receiver-node for receiving a second-receiver-signal, a first-output-node for coupling to a digital-baseband-processor, a second-output-node for coupling to the digital-baseband-processor and a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe includes a first-analog-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node and a first-ADC-output coupled to the first-output-node. The first-analog-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node and a configurable-data-pipe extending between the second-receiver-node and the second-output-node.
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公开(公告)号：US09906384B1
公开(公告)日：2018-02-27
申请号：US15275968
申请日：2016-09-26
Applicant: NXP B.V.
Inventor： Robert Rutten , Lucien Johannes Breems , Johannes Hubertus Antonius Brekelmans , Jan Niehof , Muhammed Bolatkale , Shagun Bajoria
IPC: H04L25/03
CPC classification number: H04L25/03885 , H03D3/009 , H04L27/3863 , H04L2025/0349 , H04L2025/03808
Abstract: Corrections are provided for mismatches between an in-phase (I) signal and a quadrature-phase (Q) signal, the I and Q signals having a first frequency band. A frequency filter circuit filters the I and Q signals to produce a filtered I and Q output with a second frequency band that is a subset of the first frequency band. Digital circuitry includes a multiple-tap correction filter having a plurality of taps and configured to generate I and Q output signals by filtering the I and Q signals according to respective sets of coefficients for the plurality of taps. A coefficient estimator generates the sets of coefficients relative to different frequency bands.
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Patent Agency Ranking
公开(公告)号：US20180013604A1
公开(公告)日：2018-01-11
申请号：US15619259
申请日：2017-06-09
Applicant: NXP B.V.
Inventor： Joerg Heinrich Walter Wenzel , Robert Rutten , Evert-Jan Pol , Jan van Sinderen , Tjeu van Ansem , Peter van de Haar
CPC classification number: H04L27/364 , H04L1/20 , H04L27/3863
Abstract: The disclosure relates to an IQ mismatch correction module for a radio receiver, the IQ mismatch correction module comprising: an input terminal configured to receive an input signal; an output terminal configured to provide a filtered output signal; a mismatch detection module comprising: one or more bandpass filters configured to receive, from the input terminal or output terminal, a bandpass input signal and to pass a plurality of sub-bands of the bandpass input signal to provide respective bandpass filtered signals; one or more amplitude and phase mismatch detectors configured to determine amplitude and phase mismatch coefficients based on the bandpass filtered signals from the plurality of sub-bands; a transformation unit configured to apply a transformation to the amplitude and phase mismatch coefficients to provide correction filter coefficients for the plurality of sub-bands; and a filter module configured to: receive the filter coefficients for the plurality of sub-bands from the mismatch detection module; and filter the input signal in accordance with the received filter coefficients to provide the filtered output signal.
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公开(公告)号：US12126351B2
公开(公告)日：2024-10-22
申请号：US18061601
申请日：2022-12-05
Applicant: NXP B.V.
Inventor： Robert Rutten , Muhammed Bolatkale , Lucien Johannes Breems
CPC classification number: H03M1/0621 , H03M1/1047 , H03M1/181 , H03M1/1009 , H03M1/68
Abstract: Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal. Hereby, the digital inputs provided to the DACs are non-randomized.
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公开(公告)号：US20240275365A1
公开(公告)日：2024-08-15
申请号：US18429939
申请日：2024-02-01
Applicant: NXP B.V.
Inventor： Gijsbert Willem Hardeman , Robert Rutten , Evert-Jan Daniel Pol , Qilong Liu , Shagun Bajoria , Lucien Johannes Breems
CPC classification number: H03H17/0294 , H03H17/0621 , H03H2017/0081
Abstract: A detector device for calibrating a digital filter to replicate a transfer function of a signal processing apparatus, comprising: a first input to receive a first signal; a second input configured to receive a response signal of the signal processing apparatus to the first signal; a controllable FIR filter; a comparison-block to compare the phase and amplitude after a correction has been applied by the controllable FIR filter; a feedback loop; and an interpolation-block; wherein the at least one detector is configured to determine, at least, the feedback control signal at a first frequency and at a second frequency, and wherein the interpolation-block is configured to interpolate to determine calibration information for programming of the transfer function of said digital filter.
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18.发明公开公开(公告)号：US20240048146A1
公开(公告)日：2024-02-08
申请号：US18357689
申请日：2023-07-24
Applicant: NXP B.V.
Inventor： Shagun Bajoria , Muhammed Bolatkale , Lucien Johannes Breems , Robert Rutten , Mohammed Abo Alainein
IPC: H03M1/06
CPC classification number: H03M1/0602
Abstract: A circuit 100 is described comprising (i) a first digital-to-analog converter 110, (ii) a second digital-to-analog converter 111, (iii) a plurality of unit elements 120, and (iv) switching circuitry 130. The switching circuitry 130 is adapted so that in a first switching state 231, a set of unit elements 221 of the plurality of unit elements 120 forms part of the first digital-to-analog converter 110, and in a second switching state 232, the set of unit elements 221 forms part of the second digital-to-analog converter 111. Furthermore, a corresponding method of operating a circuit 100 is described.
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公开(公告)号：US10708114B2
公开(公告)日：2020-07-07
申请号：US16122132
申请日：2018-09-05
Applicant: NXP B.V.
Inventor： Juergen Richard Marschner , Robert Rutten , Niels Gabriel , Tjeu van Ansem , Francoise Jeannette Harmsze , Peter Blinzer , Frits Anthonie Steenhof
Abstract: Certain aspects of the disclosure are directed to in-phase/quadrature (IQ) mismatch detection and correction in radio frequency receivers. According to a specific example, a method of manufacture or use comprises, in a quadrature radio-frequency receiver configured to process signals using I and Q components, providing parameters indicative of IQ mismatches associated with circuitry of the quadrature radio-frequency receiver due to changes in signal gain. The method further includes, while using the quadrature radio-frequency receiver to receive and process a received radio signal, correcting for the IQ mismatches by using the parameters in response to actual signal gain change.
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