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1.发明授权公开(公告)号：US11502699B1
公开(公告)日：2022-11-15
申请号：US17357467
申请日：2021-06-24
Applicant: NXP B.V.
Inventor： Robert Rutten , Hendrik van der Ploeg , Lucien Johannes Breems , Martin Kessel , Muhammed Bolatkale , Bernard Burdiek , Manfred Zupke , Johannes Hubertus Antonius Brekelmans , Shagun Bajoria
IPC: H03M3/00
Abstract: A digital conversion system including a sigma-delta converter, a signal generator providing a substantially symmetrical injection signal that is injected into the sigma-delta converter conversion path, bandpass filters for filtering the injection signal and the output of the sigma-delta converter, a correlator that correlates the filtered signals for providing an error signal, and a loop controller that uses the error signal to adjust a resonant frequency of the sigma-delta converter to output a target notch frequency. The loop controller may adjust a resonant frequency of a loop filter of the sigma-delta converter, in which the bandpass filters may each be centered at the target notch frequency at the output of the sigma-delta converter. The correlator may include a complex conjugate block, a multiplier and a mean calculator. The loop controller may include a converter and an amplifier and an integrator or a least-mean square block.
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公开(公告)号：US11038522B1
公开(公告)日：2021-06-15
申请号：US16779976
申请日：2020-02-03
Applicant: NXP B.V.
Inventor： Johan Frederik Witte , Lucien Johannes Breems , Robert Rutten , Muhammed Bolatkale , Johannes Hubertus Antonius Brekelmans , Shagun Bajoria , Albertus Willibrordus Oude Essink
Abstract: An apparatus including analog-to-digital conversion (ADC) circuitry is disclosed. The apparatus includes a plurality of comparators susceptible to offset variation and a shuffler circuit configured to shuffle input sources to the respective comparators. Feedback circuitry is also included and is configured and arranged with the ADC circuitry to detect offset variation in the outputs of each comparators for the shuffled inputs, relative to outputs of the plurality of comparators and compensate for the offset variation in the comparators based on the offset differences between the respective comparators.
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公开(公告)号：US10098146B2
公开(公告)日：2018-10-09
申请号：US15356451
申请日：2016-11-18
Applicant: NXP B.V.
Inventor： Jan Niehof , Shagun Bajoria , Muhammed Bolatkale , Robert Rutten , Lucien Johannes Breems , Johannes Hubertus Antonius Brekelmans
Abstract: A processor is disclosed. The processor includes a first-receiver-node for receiving a first-receiver-signal, a second-receiver-node for receiving a second-receiver-signal, a first-output-node for coupling to a digital-baseband-processor, a second-output-node for coupling to the digital-baseband-processor and a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe includes a first-analog-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node and a first-ADC-output coupled to the first-output-node. The first-analog-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node and a configurable-data-pipe extending between the second-receiver-node and the second-output-node.
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公开(公告)号：US09906384B1
公开(公告)日：2018-02-27
申请号：US15275968
申请日：2016-09-26
Applicant: NXP B.V.
Inventor： Robert Rutten , Lucien Johannes Breems , Johannes Hubertus Antonius Brekelmans , Jan Niehof , Muhammed Bolatkale , Shagun Bajoria
IPC: H04L25/03
CPC classification number: H04L25/03885 , H03D3/009 , H04L27/3863 , H04L2025/0349 , H04L2025/03808
Abstract: Corrections are provided for mismatches between an in-phase (I) signal and a quadrature-phase (Q) signal, the I and Q signals having a first frequency band. A frequency filter circuit filters the I and Q signals to produce a filtered I and Q output with a second frequency band that is a subset of the first frequency band. Digital circuitry includes a multiple-tap correction filter having a plurality of taps and configured to generate I and Q output signals by filtering the I and Q signals according to respective sets of coefficients for the plurality of taps. A coefficient estimator generates the sets of coefficients relative to different frequency bands.
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公开(公告)号：US10541699B1
公开(公告)日：2020-01-21
申请号：US16157355
申请日：2018-10-11
Applicant: NXP B.V.
Inventor： Robert Rutten , Massimo Ciacci , Manfred Zupke , Lucien Johannes Breems , Johannes Hubertus Antonius Brekelmans , Muhammed Bolatkale , Shagun Bajoria , Soheil Bahrami
Abstract: Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal.
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Patent Agency Ranking
公开(公告)号：US11522557B1
公开(公告)日：2022-12-06
申请号：US17388157
申请日：2021-07-29
Applicant: NXP B.V.
Inventor： Robert Rutten , Martin Kessel , Hendrik van der Ploeg , Lucien Johannes Breems , Muhammed Bolatkale , Evert-Jan Pol , Manfred Zupke , Bernard Burdiek , Johannes Hubertus Antonius Brekelmans , Shagun Bajoria
IPC: H03M3/00
Abstract: A digital conversion system including a sigma-delta converter, a tone generator that generates injects a tone signal into the conversion path of the sigma-delta converter at a frequency that is outside operating signal frequency range, a tone detector that isolates and detects a level of the injected tone signal and provides a corresponding tone level value, a tone ratio comparator that converts the tone level value into a tone level ratio and that compares the converted tone level ratio with an expected tone level ratio to provide an error signal, and a loop controller that converts the error signal to a correction signal to adjust a loop filter frequency the sigma-delta converter. Tones may be serially injected one at a time or simultaneously in parallel for determining a measured tone level ratio for comparison with a corresponding one of multiple stored expected tone level ratios.
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公开(公告)号：US20170150521A1
公开(公告)日：2017-05-25
申请号：US15356451
申请日：2016-11-18
Applicant: NXP B.V.
Inventor： Jan Niehof , Shagun Bajoria , Muhammed Bolatkale , Robert Rutten , Lucien Johannes Breems , Johannes Hubertus Antonius Brekelmans
CPC classification number: H04W74/002 , H03M1/0678 , H03M1/08 , H03M1/123 , H03M1/183 , H04L5/0051
Abstract: A processor is disclosed. The processor includes a first-receiver-node for receiving a first-receiver-signal, a second-receiver-node for receiving a second-receiver-signal, a first-output-node for coupling to a digital-baseband-processor, a second-output-node for coupling to the digital-baseband-processor and a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe includes a first-analogue-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node and a first-ADC-output coupled to the first-output-node. The first-analogue-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node and a configurable-data-pipe extending between the second-receiver-node and the second-output-node.
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公开(公告)号：US09419573B2
公开(公告)日：2016-08-16
申请号：US14317987
申请日：2014-06-27
Applicant: NXP B.V.
Inventor： Johannes Hubertus Antonius Brekelmans
CPC classification number: H03G3/18 , H03F1/34 , H03F3/087 , H03F3/195 , H03F3/45475 , H03F2200/336 , H03F2200/451 , H03F2203/45116 , H03F2203/45512 , H03F2203/45514 , H03F2203/45522 , H03F2203/45526 , H03F2203/45528 , H03F2203/45534 , H03F2203/45536 , H03F2203/45562 , H03F2203/45591 , H03F2203/45594 , H03F2203/45616 , H03F2203/45618 , H03F2203/45644 , H03F2203/45686 , H03F2203/45702 , H03G1/0088
Abstract: Embodiments of variable gain transimpedance amplifiers are described. In an embodiment, the variable gain transimpedance amplifier may include an amplifier coupled to an adjustable gain feedback network, the adjustable gain feedback network including a selectable set of Resistor-Capacitor (RC) branches, each RC branch having one or more unit RC elements, each unit RC element being comprised of a unit resistor and a unit capacitor arranged in parallel.
Abstract translation: 描述可变增益互阻抗放大器的实施例。 在一个实施例中，可变增益跨阻抗放大器可以包括耦合到可调增益反馈网络的放大器，所述可调增益反馈网络包括可选择的一组电阻器 - 电容器（RC）分支，每个RC分支具有一个或多个单元RC元件， 每个单元RC元件由单元电阻器和并联布置的单元电容器组成。
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公开(公告)号：US20150381129A1
公开(公告)日：2015-12-31
申请号：US14317987
申请日：2014-06-27
Applicant: NXP B.V.
Inventor： Johannes Hubertus Antonius Brekelmans
CPC classification number: H03G3/18 , H03F1/34 , H03F3/087 , H03F3/195 , H03F3/45475 , H03F2200/336 , H03F2200/451 , H03F2203/45116 , H03F2203/45512 , H03F2203/45514 , H03F2203/45522 , H03F2203/45526 , H03F2203/45528 , H03F2203/45534 , H03F2203/45536 , H03F2203/45562 , H03F2203/45591 , H03F2203/45594 , H03F2203/45616 , H03F2203/45618 , H03F2203/45644 , H03F2203/45686 , H03F2203/45702 , H03G1/0088
Abstract: Embodiments of variable gain transimpedance amplifiers are described. In an embodiment, the variable gain transimpedance amplifier may include an amplifier coupled to an adjustable gain feedback network, the adjustable gain feedback network including a selectable set of Resistor-Capacitor (RC) branches, each RC branch having one or more unit RC elements, each unit RC element being comprised of a unit resistor and a unit capacitor arranged in parallel.
Abstract translation: 描述可变增益互阻抗放大器的实施例。 在一个实施例中，可变增益跨阻抗放大器可以包括耦合到可调增益反馈网络的放大器，所述可调增益反馈网络包括可选择的一组电阻器 - 电容器（RC）分支，每个RC分支具有一个或多个单元RC元件， 每个单元RC元件由单元电阻器和并联布置的单元电容器组成。
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公开(公告)号：US08922288B2
公开(公告)日：2014-12-30
申请号：US13774163
申请日：2013-02-22
Applicant: NXP B.V.
CPC classification number: H03L5/00 , H03B5/06 , H03B5/12 , H03B5/1212 , H03B5/124 , H03B5/36 , H03L3/00
Abstract: An oscillator circuit comprising first and second resonator terminals for connecting to respective terminals of a resonator. The oscillator circuit also comprises a first inverting amplifier connected between the first and second resonator terminals in a first mode of operation; and a back to back pair of second inverting amplifiers connected between the first and second resonator terminals in a second mode of operation. There is also provided a controller configured to compare an operational parameter of the oscillator circuit to a switchover threshold, and switch the oscillator circuit from the first mode of operation to the second mode of operation when the operational parameter exceeds the switchover threshold.
Abstract translation: 一种振荡器电路，包括用于连接到谐振器的各个端子的第一和第二谐振器端子。 振荡器电路还包括在第一操作模式下连接在第一和第二谐振器端子之间的第一反相放大器; 以及在第二操作模式下连接在第一和第二谐振器端子之间的背靠背对的第二反相放大器。 还提供了一种控制器，被配置为将振荡器电路的操作参数与切换阈值进行比较，并且当操作参数超过切换阈值时，将振荡器电路从第一操作模式切换到第二操作模式。
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