公开(公告)号：US11941281B2

公开(公告)日：2024-03-26

申请号：US17711968

申请日：2022-04-01

Applicant: NXP B.V.

Inventor： Soenke Ostertun

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0616 ,  G06F3/0658 ,  G06F3/0679

Abstract: A system and method for a memory system are provided. A memory device includes an array of non-volatile memory cells. A memory controller is connected to the array of non-volatile memory cells. The memory controller is configured to perform the steps of receiving a request to read a value of a memory flag, wherein the memory flag includes a 2-bit value stored in a first memory cell and a second memory cell of the array of non-volatile memory cells, reading a first value of the first memory cell, reading a second value of the second memory cell, and determining the value of the memory flag based on the first value and the second value. In embodiments, the memory flag may have more than 2-bits.

公开(公告)号：US11694761B2

公开(公告)日：2023-07-04

申请号：US17477871

申请日：2021-09-17

Applicant: NXP B.V.

Inventor： Soenke Ostertun ,  Bjorn Fay ,  Vitaly Ocheretny

IPC: G11C29/42 ,  G06F11/10

CPC classification number: G11C29/42 ,  G06F11/1056 ,  G06F11/1068 ,  G06F11/1096

Abstract: Various embodiments relate to a method for storing and reading data from a memory. Data words stored in the memory may be grouped, and word specific parity information and shared parity information is generated, and the shared parity information is distributed among the group of words. During reading of a word, if more errors are detected than can be corrected with word parity data, the shared parity data is retrieved and used to make the error corrections.

公开(公告)号：US20230089443A1

公开(公告)日：2023-03-23

申请号：US17477871

申请日：2021-09-17

Applicant: NXP B.V.

Inventor： Soenke Ostertun ,  Bjorn Fay ,  Vitaly Ocheretny

IPC: G11C29/42 ,  G06F11/10

Abstract: Various embodiments relate to a method for storing and reading data from a memory. Data words stored in the memory may be grouped, and word specific parity information and shared parity information is generated, and the shared parity information is distributed among the group of words. During reading of a word, if more errors are detected than can be corrected with word parity data, the shared parity data is retrieved and used to make the error corrections.

公开(公告)号：US10657294B2

公开(公告)日：2020-05-19

申请号：US16581855

申请日：2019-09-25

Applicant: NXP B.V.

Inventor： Christoph Hans Joachim Garbe ,  Soenke Ostertun

IPC: H03K19/00 ,  G06F21/79 ,  H04L9/08 ,  G11C16/04

Abstract: In accordance with a first aspect of the present disclosure, a non-volatile memory is provided, comprising: a plurality of storage elements; a plurality of access transistors, said access transistors being connected to one or more of said storage elements; a measurement unit, wherein said measurement unit is configured to measure a variation between electrical characteristics of said access transistors; a processing unit configured to use said variation between electric characteristics as a physical unclonable function. In accordance with a second aspect of the present disclosure, a corresponding method of manufacturing a non-volatile memory is conceived.

公开(公告)号：US09509306B2

公开(公告)日：2016-11-29

申请号：US13866864

申请日：2013-04-19

Applicant: NXP B.V.

Inventor： Soenke Ostertun ,  Michael Ziesmann

IPC: H03K19/003 ,  H01L23/00 ,  H01L21/306

CPC classification number: H03K19/003 ,  H01L21/306 ,  H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said integrated circuit. According to a further aspect of the invention, a corresponding method for manufacturing an integrated circuit is conceived. According to a further aspect of the invention, an electronic device is conceived which comprises an integrated circuit of the kind set forth.

Abstract translation: 根据本发明的一个方面，构思了一种集成电路，其包括至少部分地在所述集成电路的钝化层中实现的物理不可克隆功能。 根据本发明的另一方面，构思了用于制造集成电路的相应方法。 根据本发明的另一方面，构思了包括所述类型的集成电路的电子设备。

公开(公告)号：US09471792B2

公开(公告)日：2016-10-18

申请号：US14010145

申请日：2013-08-26

Applicant: NXP B.V.

Inventor： Soenke Ostertun ,  Joachim Christoph Hans Garbe

IPC: G06F11/22 ,  G06F17/50 ,  G06F21/60 ,  G06K19/073

CPC classification number: G06F21/60 ,  G06K19/07372

Abstract: There is provided a detection arrangement for detecting an attack to internal signals in a semiconductor device. The detection arrangement comprises a first input terminal, a second input terminal, and a comparison unit. The first input terminal is adapted to receive a first signal being indicative for a signal at a first stage of a driver of the semiconductor device, the driver being capable to drive signals internally to the semiconductor device. The second input terminal is adapted to receive a second signal being indicative for a signal at a second stage of the driver of the semiconductor device. The comparison unit is adapted to compare the first signal and the second signal and to determine a time period during which the signals are equal, wherein the determined time period is indicative for a potential attack, if the determined time period is above a predefined threshold.

Abstract translation: 提供了用于检测对半导体器件中的内部信号的攻击的检测装置。 检测装置包括第一输入端子，第二输入端子和比较单元。 第一输入端子适于接收指示半导体器件的驱动器的第一级处的信号的第一信号，该驱动器能够在半导体器件内部驱动信号。 第二输入端子适于接收在半导体器件的驱动器的第二级指示信号的第二信号。 所述比较单元适于比较所述第一信号和所述第二信号，并且确定所述信号相等的时间段，其中如果所确定的时间段高于预定阈值，则确定的时间段指示潜在的攻击。

公开(公告)号：US09454471B2

公开(公告)日：2016-09-27

申请号：US14029659

申请日：2013-09-17

Applicant: NXP B.V.

Inventor： Martin Feldhofer ,  Franz Amtmann ,  Soenke Ostertun ,  Alicia da Conceicao

IPC: G06F12/00 ,  H03K21/40

CPC classification number: G06F12/00 ,  H03K21/403

Abstract: An electronic counter is provided having a sequence of memory cells and increment logic. Each memory cell of the sequence is non-volatile and supports a one state and a zero state. The one state can also be referred to as a ‘programmed state’, the zero state as an ‘erased state’. The counter is configured to represent at least part of a current counting-state of the counter as a pattern of one and zero states in the memory cells of the sequence of memory cells, and increment logic configured to advance the pattern of one and zero states to a next pattern to represent an increment of the counter.

Abstract translation: 提供了具有一系列存储单元和增量逻辑的电子计数器。 序列的每个存储单元是非易失性的，并且支持一个状态和一个零状态。 一个状态也可以被称为“编程状态”，零状态被称为“擦除状态”。 计数器被配置为将计数器的当前计数状态的至少一部分表示为存储器单元序列的存储单元中的一个和零个状态的模式，并且增量逻辑被配置为提前一个和零个状态的模式 到下一个模式来表示计数器的增量。