公开(公告)号：US10790850B1

公开(公告)日：2020-09-29

申请号：US16456365

申请日：2019-06-28

Applicant: NXP B.V.

Inventor： Yu Lin ,  Vladislav Dyachenko

IPC: H03M1/20 ,  H03M3/00 ,  H03M1/46

Abstract: An analog-to-digital converter (ADC) and a method are disclosed. The ADC includes dithering circuitry. The dithering circuitry includes a signal level detector, a dither amplitude controller, a random code generator, and a dither digital-to-analog converter (DAC). The signal level detector receives the analog input signal and provides amplitude level information associated with the analog input signal. The dither amplitude controller receives the amplitude level information from the signal level detector, and provides a control signal. The dither amplitude controller varies the control signal based on the amplitude level information. The dither DAC receives the control signal from the dither amplitude controller and a pseudo-noise (PN) signal from the random code generator, and provides the dither signal based on the control signal. The dither signal varies based on an amplitude level of the analog input signal.

公开(公告)号：US10469095B2

公开(公告)日：2019-11-05

申请号：US16119117

申请日：2018-08-31

Applicant: NXP B.V.

Inventor： Yu Lin ,  Erwin Janssen ,  Vladislav Dyachenko

IPC: H03M1/38 ,  H03M1/18 ,  G01S13/06 ,  H03M1/10 ,  H03M1/46

Abstract: A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460). The DAC (430) is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller (418) is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC (430) and the digital signal reconstruction circuit (450) to implement a small signal mapping mode of operation.

公开(公告)号：US10361710B2

公开(公告)日：2019-07-23

申请号：US16031988

申请日：2018-07-10

Applicant: NXP B.V.

Inventor： Yu Lin ,  Marcello Ganzerli

IPC: H03M1/12 ,  H03M1/00 ,  H04B1/3805 ,  H03M1/16 ,  H04B1/401 ,  H03M1/18

Abstract: The present application relates to a reconfigurable analog front-end circuit and a reconfigurable Ethernet transceiver with a reconfigurable analog front-end circuit. The circuit is reconfigurable using the at least one signal-path switching element controlled by a mode signal to operationally establish a first or a second signal path. The first signal path comprises an optional first signal-conditioning section and a shared ADC. The second signal path comprises an optional second signal-conditioning section, an upstream ADC and the shared ADC. The signal paths are selectively switched in response to a mode signal.

公开(公告)号：US20180183471A1

公开(公告)日：2018-06-28

申请号：US15847964

申请日：2017-12-20

Applicant: NXP B.V.

Inventor： Yu Lin

IPC: H04B1/10 ,  H03M1/18 ,  G01S13/34 ,  G01S7/292 ,  G01S13/28 ,  G01S7/03 ,  G01S13/44 ,  G01S13/93

CPC classification number: H04B1/109 ,  G01S7/038 ,  G01S7/292 ,  G01S7/354 ,  G01S13/286 ,  G01S13/34 ,  G01S13/348 ,  G01S13/4454 ,  G01S13/931 ,  G01S2013/9325 ,  H03M1/188

Abstract: A receive path arrangement of a radar sensor of FMCW type comprising a first and second receive path configured to receive reflected radar signals for detection and ranging of objects in a space around the radar sensor; the first receive path configured to provide reflected radar signals between a first and second beat frequency to a first analogue to digital converter for subsequent digital signal processing and wherein; the second receive path includes a second-receive-path filter configured to provide filtered signals by attenuation of the reflected radar signals having frequencies below an intermediate beat frequency, the intermediate beat frequency between the first and second beat frequencies, the second receive path further including a second-receive-path amplifier arrangement configured to provide amplified signals by amplification of the filtered signals and provide the amplified signals to a second analogue to digital converter for subsequent digital signal processing.