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    FIELD PLATE STRUCTURES FOR GAN HIGH VOLTAGE TRANSISTORS
    14.
    发明申请
    FIELD PLATE STRUCTURES FOR GAN HIGH VOLTAGE TRANSISTORS 有权

    公开(公告)号：US20220384586A1

    公开(公告)日：2022-12-01

    申请号：US17829905

    申请日：2022-06-01

    Applicant: Navitas Semiconductor Limited

    Inventor： Pil Sung Park ,  Daniel M. Kinzer

    IPC: H01L29/40 ,  H01L29/778 ,  H01L29/20

    Abstract: Field plate structures for gallium nitride (GaN) high voltage transistors are disclosed. In one aspect, a transistor includes a GaN substrate, a source region formed on the GaN substrate, a drain region formed on the GaN substrate and separate from the source region, a gate region formed between the source region and the drain region, a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, and a field plate electrically coupled to the source region, where the field plate extends from a proximal region positioned between the source region and the pedestal, towards the drain region, where at least a portion of the field plate overlaps at least a portion of the pedestal.

    ELECTRONIC PACKAGES WITH INTEGRAL HEAT SPREADERS
    15.
    发明申请
    ELECTRONIC PACKAGES WITH INTEGRAL HEAT SPREADERS 有权

    公开(公告)号：US20220310475A1

    公开(公告)日：2022-09-29

    申请号：US17702694

    申请日：2022-03-23

    Applicant: Navitas Semiconductor Limited

    Inventor： Charles Bailley ,  George Chu ,  Daniel M. Kinzer

    IPC: H01L23/367 ,  H01L25/07 ,  H01L21/48 ,  H01L25/00

    Abstract: An electronic device includes a substrate and a first gallium nitride (GaN) transistor formed on a first semiconductor die that is electrically coupled to the substrate. A second GaN transistor is formed on a second semiconductor die and is also electrically coupled to the substrate. An integral heat spreader is thermally coupled to the first and the second gallium nitride semiconductor dies and is electrically coupled to the substrate. A first bias voltage is applied to the first GaN transistor via the integral heat spreader and a second bias voltage is applied to the second GaN transistor via the integral heat spreader.

    MONOLITHIC HIGH SIDE GALLIUM NITRIDE DEVICE WITH INTEGRATED CAPACITIVE LEVEL SHIFTER CIRCUITS
    18.
    发明申请
    MONOLITHIC HIGH SIDE GALLIUM NITRIDE DEVICE WITH INTEGRATED CAPACITIVE LEVEL SHIFTER CIRCUITS 有权

    公开(公告)号：US20230139736A1

    公开(公告)日：2023-05-04

    申请号：US18051799

    申请日：2022-11-01

    Applicant: Navitas Semiconductor Limited

    Inventor： Marco Giandalia ,  Santosh Sharma ,  Jung Hee Lee ,  Daniel M. Kinzer

    IPC: H01L27/06 ,  H02M3/00 ,  H02M1/08

    Abstract: Monolithic high side GaN-based circuits using capacitors for level shifting. In one aspect, a power converter includes a GaN-based die, a switch formed on the GaN-based die and having a gate terminal, where the switch is arranged to be selectively conductive according to a driver signal applied to the gate terminal, a buffer circuit formed on the GaN-based die and arranged to receive an input signal and generate a corresponding differential output signal at a first output terminal and at a second output terminal, and a voltage level converter formed on the GaN-based die and having a first input terminal coupled to the first output terminal via a first capacitor and having a second input terminal coupled to the second output terminal via a second capacitor, where the first and second capacitors are formed on the GaN-based die, and the voltage level converter is arranged to generate the driver signal.

    SYSTEM AND METHODS FOR SINGULATION OF GAN-ON-SILICON WAFERS
    20.
    发明申请
    SYSTEM AND METHODS FOR SINGULATION OF GAN-ON-SILICON WAFERS 有权

    公开(公告)号：US20230013188A1

    公开(公告)日：2023-01-19

    申请号：US17812385

    申请日：2022-07-13

    Applicant: Navitas Semiconductor Limited

    Inventor： George Chu ,  Nick Fichtenbaum ,  Kai-Ling Chiu ,  Daniel M. Kinzer ,  Maher Hamdan ,  Pil Sung Park

    IPC: H01L21/78 ,  H01L23/522

    Abstract: Structures and related techniques for singulating GaN-on-Si wafers are disclosed. In one aspect, a semiconductor wafer includes a silicon layer, and a gallium nitride (GaN) layer disposed on the silicon layer and defining a plurality of trenches that each extend to the silicon layer. In another aspect, the GaN layer includes one or more gallium nitride layers of different compositions. In yet another aspect, the wafer includes a plurality of dielectric layers disposed on the GaN layer. In yet another aspect, each of the plurality of trenches has a depth that is equal to a sum of a thickness of the GaN layer and a thickness of the plurality of the dielectric layers.

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