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公开(公告)号：US07313060B2
公开(公告)日：2007-12-25
申请号：US10523386
申请日：2003-07-21
IPC分类号： G11B7/00
CPC分类号： G11B20/10027 , G11B7/005 , G11B20/10009 , G11B2020/1288 , G11B2220/2541
摘要： An optical disk system includes at least one photo detector connected with a variable gain amplifier, a slicer, and a generator which is in the feedback path between the slicer and amplifier. A differential time delay detector provides the output of the optical disk system. The generator is configured for controlling the amplifier non-linearly so that time constants of the control loop of the amplifier which depend upon the level of the input signals are compensated and the timing behavior of the control loop of the amplifier has a more continuous character. A capacitor forms part of an integrator for making the mean value of the output voltage signal of the slicer equal to zero.
摘要翻译： 光盘系统包括与可变增益放大器，限幅器和发生器连接的至少一个光电检测器，该可变增益放大器，限幅器和发生器处于限幅器和放大器之间的反馈路径中。 差分延时检测器提供光盘系统的输出。 发生器被配置为非线性地控制放大器，使得取决于输入信号的电平的放大器的控制环路的时间常数被补偿，并且放大器的控制环路的定时特性具有更连续的特性。 电容器形成积分器的一部分，用于使限幅器的输出电压信号的平均值等于零。
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12.发明授权Arrangement for calibrating the quiescent operating point of a push-pull amplifier 有权用于校准推挽放大器的静态工作点的布置公开(公告)号：US08354886B2
公开(公告)日：2013-01-15
申请号：US13058276
申请日：2009-08-10
IPC分类号： H03F3/26
CPC分类号： H03F1/308 , H03F1/3217 , H03F3/3028 , H03F3/345 , H03F2203/30003 , H03F2203/30033
摘要： A signal processing arrangement comprises an amplifier (AMP V1) that includes a stage with complementary transistors (MP3, MN3) of opposite conductivity type arranged in series between two supply lines (+, −). A controllable biasing circuit (CCS) is provided for changing a quiescent operating point of the stage as a function of a control signal (CS). A control arrangement measures an even order 5 distortion of the amplifier (AMP V1) and adjusts the control signal (CS) so that the even order distortion is below a critical level.
摘要翻译： 信号处理装置包括放大器（AMP V1），放大器（AMP V1）包括具有串联布置在两条电源线（+， - ）之间的相反导电类型的互补晶体管（MP3，MN3）的平台。 提供了可控偏置电路（CCS），用于根据控制信号（CS）来改变级的静态工作点。 控制装置测量放大器（AMP V1）的偶数阶失真5并调整控制信号（CS），使偶数阶失真低于临界水平。
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公开(公告)号：US08135375B2
公开(公告)日：2012-03-13
申请号：US12065315
申请日：2006-08-23
IPC分类号： H04B1/16
CPC分类号： H03G3/3052
摘要： A gain-controllable stage (CLN, A1, A2 . . . , A7, ACC) comprises a reactive signal divider (CLN) followed by an amplifier arrangement (A1, A2 . . . , A7, ACC). The reactive signal divider (CLN) may be in the form of, for example, a capacitive ladder network. The gain-controllable stage (CLN, A1, A2 . . . , A7, ACC) has a gain factor that depends on a signal division factor that the reactive signal divider (CLN) provides. The reactive signal divider (CLN) forms part of a filter (LC). The signal division factor is adjusted on the basis of a frequency (F) to which the receiver is tuned and a signal-strength indication (RS).
摘要翻译： 增益可控级（CLN，A1，A2 ...，A7，ACC）包括一个无功信号分频器（CLN），后面是一个放大器装置（A1，A2 ... A7，ACC）。 无功信号分配器（CLN）可以是例如电容梯形网络的形式。 增益可控级（CLN，A1，A2 ... A7，ACC）具有取决于无功信号分频器（CLN）提供的信号分配因子的增益因子。 无功信号分频器（CLN）形成滤波器（LC）的一部分。 基于接收机调谐的频率（F）和信号强度指示（RS）来调整信号分配因子。
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14.发明申请ARRANGEMENT FOR CALIBRATING THE QUIESCENT OPERATING POINT OF A PUSH-PULL AMPLIFIER 有权用于校准推拉放大器的等效工作点的布置公开(公告)号：US20110133839A1
公开(公告)日：2011-06-09
申请号：US13058276
申请日：2009-08-10
IPC分类号： H03F3/26
CPC分类号： H03F1/308 , H03F1/3217 , H03F3/3028 , H03F3/345 , H03F2203/30003 , H03F2203/30033
摘要： A signal processing arrangement comprises an amplifier (AMP V1) that includes a stage with complementary transistors (MP3, MN3) of opposite conductivity type arranged in series between two supply lines (+, −). A controllable biasing circuit (CCS) is provided for changing a quiescent operating point of the stage as a function of a control signal (CS). A control arrangement measures an even order 5 distortion of the amplifier (AMP V1) and adjusts the control signal (CS) so that the even order distortion is below a critical level.
摘要翻译： 信号处理装置包括放大器（AMP V1），放大器（AMP V1）包括具有串联布置在两条电源线（+， - ）之间的相反导电类型的互补晶体管（MP3，MN3）的平台。 提供了可控偏置电路（CCS），用于根据控制信号（CS）来改变级的静态工作点。 控制装置测量放大器（AMP V1）的偶数阶失真5并调整控制信号（CS），使偶数阶失真低于临界水平。
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15.发明申请DEVICE FOR RECEIVING A RF SIGNAL WITH LOOP-THROUGH OUTPUT AND METHOD FOR LOOPING A RF INPUT SIGNAL THROUGH A DEVICE FOR RECEIVING RF SIGNALS 有权用于接收具有环绕输出的RF信号的设备和用于通过用于接收RF信号的设备来循环RF输入信号的方法公开(公告)号：US20100302082A1
公开(公告)日：2010-12-02
申请号：US12744693
申请日：2008-11-24
IPC分类号： H03M1/00
摘要： A device for receiving a RF signal (1; 21) with loop-through output (16) is provided. The device comprises: an input (3) receiving a RF input signal (2); an analog-digital converter (8) converting the RF input signal (2) to a digital signal (9); a digital signal processing unit (10) digitally processing the digital signal (9); a digital-analog converter (14) converting the processed digital signal (13) to a loop-through RF signal (15) corresponding to the RF input signal (2); and a loop-through output (16) outputting the loop-through RF signal (15).
摘要翻译： 提供了一种用于接收具有环通输出（16）的RF信号（1; 21）的装置。 该装置包括：接收RF输入信号的输入端（3）; 将所述RF输入信号（2）转换为数字信号（9）的模拟数字转换器（8）; 数字信号处理单元（10）数字处理数字信号（9）; 将经处理的数字信号（13）转换成对应于RF输入信号（2）的环通RF信号（15）的数模转换器（14）; 以及输出环通RF信号（15）的环路输出（16）。
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公开(公告)号：US20090278603A1
公开(公告)日：2009-11-12
申请号：US11577308
申请日：2005-10-13
CPC分类号： G05F3/262
摘要： The present invention relates to an all n-type transistor current mirror for mirroring an input current to an output current. The current mirror comprises an input n-type transistor (T4, QO, T1) interposed between a positive supply plane (VCC) and an input node (104, 202, 310) with its collector being connected to the positive supply plane (VCC) and its emitter being connected to the input node (104, 202, 310). An output n-type transistor (T3, Q1, T2) is interposed between the positive supply plane (VCC) and an output node (106, 204, 314) with its collector being connected to the positive supply plane (VCC) and its emitter being connected to the output node (106, 204, 314). A feedback circuit equals base-emitter voltages of the input (T4, QO, T1) and the output transistor (T3, Q1, T2) in order to mirror the emitter current of the input transistor (T4, QO, T1) to the emitter current of the output transistor (T3, Q1, T2). The all n-type transistor current mirror is highly advantageous by overcoming the shortcomings of technologies such as MOBI3, GaAs, and InP of being unable to provide p-type transistors.
摘要翻译： 本发明涉及用于将输入电流镜像到输出电流的全n型晶体管电流镜。 电流镜包括插入正电源平面（VCC）和输入节点（104,202,310）之间的输入n型晶体管（T4，QO，T1），其集电极连接到正电源平面（VCC） 并且其发射极连接到输入节点（104,202,310）。 输出n型晶体管（T3，Q1，T2）介于正电源平面（VCC）和输出节点（106,204,314）之间，其集电极连接到正电源平面（VCC）及其发射极 连接到输出节点（106,204,314）。 反馈电路等于输入（T4，QO，T1）和输出晶体管（T3，Q1，T2）的基极 - 发射极电压，以便将输入晶体管（T4，QO，T1）的发射极电流镜像到发射极 输出晶体管（T3，Q1，T2）的电流。 所有n型晶体管电流镜通过克服诸如MOBI3，GaAs和InP等不能提供p型晶体管的技术的缺点是非常有利的。
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17.发明授权公开(公告)号：US07248107B2
公开(公告)日：2007-07-24
申请号：US10552817
申请日：2004-04-08
IPC分类号： H03G3/20
CPC分类号： H03G1/0088
摘要： The present invention relates to a method of controlling a variable gain amplifier having at least one semiconductor switch, the amplifier having a first gain when the semiconductor switch is in a first steady state and a first gate voltage is applied to the semiconductor switch, and the amplifier having a second gain when the semiconductor switch is in a second steady state and a second gate voltage is applied to the semiconductor switch, whereby a sequence of third gate voltages is applied to the semiconductor switch to transition between the first and second gains.
摘要翻译： 本发明涉及一种控制具有至少一个半导体开关的可变增益放大器的方法，当半导体开关处于第一稳定状态并且第一栅极电压施加到半导体开关时，放大器具有第一增益，并且 放大器，当半导体开关处于第二稳定状态并且第二栅极电压被施加到半导体开关时具有第二增益，由此一系列第三栅极电压被施加到半导体开关以在第一和第二增益之间转变。
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公开(公告)号：US07038434B1
公开(公告)日：2006-05-02
申请号：US10523730
申请日：2003-07-21
IPC分类号： G05F1/40
CPC分类号： G05F1/575
摘要： A low dropout voltage regulator comprising a series-regulating element (T1) between an input (I) and an output (O) of the voltage regulator, and a differential input error amplifier (1) having a first output (O1) coupled to a control input of the series-regulating element (T1), characterized in that the error amplifier (1) further comprises a second output (O2) coupled to the output (O) via a high-pass filter (5, C1, R1).
摘要翻译： 一种低压降稳压器，包括在电压调节器的输入（I）和输出（O）之间的串联调节元件（T 1）和差分输入误差放大器（1），其具有耦合的第一输出（O 1） 到串联调节元件（T 1）的控制输入端，其特征在于误差放大器（1）还包括经由高通滤波器（5，C）耦合到输出端（O）的第二输出端（O 2） 1，R 1）。
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公开(公告)号：US20110115539A1
公开(公告)日：2011-05-19
申请号：US13002818
申请日：2009-07-07
IPC分类号： H03H11/26
CPC分类号： H03K23/54
摘要： A signal processing arrangement comprises a series of latches (XDL, L1, L2) arranged as a clocked delay line (CDL) having a data input and a data output that are coupled to each other so as to form an inverting loop. An enable circuit (ACDL) allows or prevents a latch (L2) in the series of latches from changing state depending on whether, one clock cycle ago, the latch concerned received a given binary value or the inverse of that given binary 5 value, respectively, from the preceding latch (L1) in the series of latches. Such a circuit configuration allows a low-cost frequency division by an odd number with relatively small duty cycle errors.
摘要翻译： 信号处理装置包括被布置为具有数据输入的时钟延迟线（CDL）的一系列锁存器（XDL，L1，L2）和彼此耦合以形成反相环路的数据输出。 使能电路（ACDL）允许或防止一系列锁存器中的锁存器（L2）根据一个时钟周期之前的锁存器是否分别接收到给定的二进制值或者给定的二进制值5的反相来改变状态 ，从一系列闩锁中的先前锁存（L1）开始。 这种电路配置允许以相对小的占空比误差的低成本分频奇数。
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公开(公告)号：US07499694B1
公开(公告)日：2009-03-03
申请号：US09890490
申请日：2000-11-27
CPC分类号： H03J3/08 , H03J1/0033 , H04N5/50 , H04N21/4383 , H04N21/44209
摘要： In a method of tuning a receiver for a digital signal (MPEG2-TS), an input signal (RF-in) is filtered (In-filt, Band-filt) to obtain a processed signal, a digital figure of merit (BER) is determined (Mix/Osc/IF amp IF-downconv-2, C) from the processed signal, and the filtering step (In-filt, Band-filt) is fine-adjusted (μP, PLL, DAC1-DAC3) in dependence on the digital figure of merit (BER).
摘要翻译： 在对数字信号（MPEG2-TS）的接收机进行调谐的方法中，对输入信号（RF-in）进行滤波（滤波，频带滤波）以获得经处理的信号，数字品质因数（BER） 从处理信号中确定（Mix / Osc / IF amp IF-downconv-2，C），依次对滤波步骤（In-filt，Band-filt）进行微调（muP，PLL，DAC1-DAC3） 关于数字品质因数（BER）。
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