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17 条记录 (耗时 0.026 秒)

    Method of making a semiconductor memory device
    11.
    发明授权
    Method of making a semiconductor memory device 失效
    制造半导体存储器件的方法

    公开(公告)号：US5312769A

    公开(公告)日：1994-05-17

    申请号：US47110

    申请日：1993-04-13

    申请人： Naoto Matsuo ,  Shouzou Okada

    发明人： Naoto Matsuo ,  Shouzou Okada

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10852 ,  H01L28/40

    摘要： A semiconductor memory device in which a storage electrode of a storage capacitor of a memory cell is formed by a selective chemical vapor deposition (CVD) technique. A lithography process is not required when forming the storage electrode. There is no narrowing of the storage electrode pattern and the minimum distance between adjacent storage electrodes can be made smaller than the minimum wiring dimension. The storage capacitance of the semiconductor memory device can be increased and a high storage capacitance is obtained.

    摘要翻译： 一种通过选择性化学气相沉积（CVD）技术形成存储单元的存储电容器的存储电极的半导体存储器件。 在形成存储电极时不需要光刻工艺。 存储电极图案不会变窄，并且可以使相邻的存储电极之间的最小距离小于最小布线尺寸。 可以增加半导体存储器件的存储电容并获得高的存储电容。

    Thin-film semiconductor device and method of fabricating the same
    12.
    发明授权
    Thin-film semiconductor device and method of fabricating the same 失效
    薄膜半导体器件及其制造方法

    公开(公告)号：US5214296A

    公开(公告)日：1993-05-25

    申请号：US848840

    申请日：1992-03-10

    申请人： Yoshiro Nakata ,  Naoto Matsuo ,  Toshiki Yabu ,  Susumu Matsumoto ,  Shozo Okada

    发明人： Yoshiro Nakata ,  Naoto Matsuo ,  Toshiki Yabu ,  Susumu Matsumoto ,  Shozo Okada

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L29/786

    CPC分类号： H01L29/78642 ,  H01L27/10817

    摘要： A thin-film semiconductor device having a vertical TFT which includes a gate insulating film formed on a sidewall of a throughhole formed in an insulating layer; a thin-film semiconductor layer formed on the gate insulating film; and a gate electrode formed within the insulating layer. The gate electrode, the gate insulating film, and the thin-film semiconductor layer together form a lateral MOS structure. The thin-film semiconductor layer is connected to a bit line at the bottom of the throughhole and to a storage node of a capacitor formed over the switching transistor.

    摘要翻译： 一种具有垂直TFT的薄膜半导体器件，其包括形成在绝缘层中形成的通孔的侧壁上的栅极绝缘膜; 形成在所述栅极绝缘膜上的薄膜半导体层; 以及形成在所述绝缘层内的栅电极。 栅电极，栅极绝缘膜和薄膜半导体层一起形成横向MOS结构。 薄膜半导体层连接到通孔底部的位线和形成在开关晶体管上的电容器的存储节点。

    IMAGE FORMING APPARATUS
    15.
    发明申请
    IMAGE FORMING APPARATUS 审中-公开
    图像形成装置

    公开(公告)号：US20070188584A1

    公开(公告)日：2007-08-16

    申请号：US11673267

    申请日：2007-02-09

    申请人： Tetsurou Nakamura ,  Kei Sakanoue ,  Yuuji Toyomura ,  Ryuuichi Yatsunami ,  Takafumi Hamano ,  Naoto Matsuo ,  Shinya Yamamoto

    发明人： Tetsurou Nakamura ,  Kei Sakanoue ,  Yuuji Toyomura ,  Ryuuichi Yatsunami ,  Takafumi Hamano ,  Naoto Matsuo ,  Shinya Yamamoto

    IPC分类号： B41J2/385

    CPC分类号： B41J2/45

    摘要： An image forming apparatus includes a photoconductor 8 which bears an image to be formed by exposure, a light emission part 600 which emits light for exposing the photoconductor 8 to the light, and a light quantity measuring part 700 which measures the quantity of the light emitted from the light emission part 600 and outputs a light quantity measuring signal. The light quantity measuring signal of the light quantity measuring part 700 is sent through an engine control part 42 to a controller 41, and the quantity of the light emitted from the light emission part 600 is controlled so that the light quantity measuring signal becomes a predetermined value. Here, a sign indicating inclination (change rate) of the light quantity measuring signal of the light quantity measuring part 700 for temperature is matched with a sign indicating inclination (change rate) of sensitivity of the photoconductor 8 for temperature.

    摘要翻译： 图像形成装置包括承载要通过曝光形成的图像的光电导体8，发射用于将光电导体8暴露于光的光的发光部600和测量发光量的光量测量部700 从光发射部600输出光量测量信号。 光量测量部700的光量测量信号通过发动机控制部分42发送到控制器41，并且控制从发光部分600发射的光量，使得光量测量信号变为预定的 值。 这里，指示用于温度的光量测量部件700的光量测量信号的倾斜度（变化率）的符号表示用于温度的光电导体8的灵敏度的倾斜度（变化率）。

    Semiconductor memory device in which a capacitor electrode of a memory cell and an interconnection layer of a peripheral circuit are formed in one level
    16.
    发明授权
    Semiconductor memory device in which a capacitor electrode of a memory cell and an interconnection layer of a peripheral circuit are formed in one level 失效
    半导体存储器件，其中存储单元的电容器电极和外围电路的互连层形成在一个级中

    公开(公告)号：US5399890A

    公开(公告)日：1995-03-21

    申请号：US257955

    申请日：1994-06-10

    申请人： Shozo Okada ,  Hisashi Ogawa ,  Naoto Matsuo ,  Yoshiro Nakata ,  Toshiki Yabu ,  Susumu Matsumoto

    发明人： Shozo Okada ,  Hisashi Ogawa ,  Naoto Matsuo ,  Yoshiro Nakata ,  Toshiki Yabu ,  Susumu Matsumoto

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78

    CPC分类号： H01L27/105 ,  H01L27/10808

    摘要： A semiconductor memory of the invention includes a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of the plurality of transistors, a plurality of first level interconnection layers connected to other portions of the plurality of transistors, and a plurality of second level interconnection layers disposed above the stacked capacitors and the first level interconnection layers. Each of the plurality of stacked capacitors includes a first electrode layer, a capacitance insulating film formed on top of the first electrode layer, and a second electrode layer formed on top of the capacitance insulating film. The second electrode layer is connected to a portion of one of the plurality of second level interconnection layers. At least portions of the plurality of first level interconnection layers are connected to other portions of the plurality of second level interconnection layers. Each of the plurality of first level interconnection layers shares the same layer as at least one of the first electrode layer and the second electrode layer.

    摘要翻译： 本发明的半导体存储器包括具有多个晶体管的半导体衬底，与多个晶体管的一部分连接的多个叠层电容器，与多个晶体管的其它部分连接的多个第一级互连层，以及多个晶体管的多个 位于层叠电容器和第一级互连层之上的第二级互连层。 多个叠层电容器中的每一个包括第一电极层，形成在第一电极层顶部的电容绝缘膜，以及形成在电容绝缘膜顶部的第二电极层。 第二电极层连接到多个第二级互连层之一的一部分。 多个第一级互连层的至少一部分连接到多个第二级互连层的其它部分。 多个第一级互连层中的每一个与第一电极层和第二电极层中的至少一个共享相同的层。

    Method for making semiconductor integration circuit with stacked capacitor cells
    17.
    发明授权
    Method for making semiconductor integration circuit with stacked capacitor cells 失效
    具有层叠电容器单元的半导体积分电路的方法

    公开(公告)号：US5217914A

    公开(公告)日：1993-06-08

    申请号：US683603

    申请日：1991-04-10

    申请人： Susumu Matsumoto ,  Toshiki Yabu ,  Yoshiro Nakata ,  Naoto Matsuo ,  Shozo Okada ,  Hiroyuki Sakai

    发明人： Susumu Matsumoto ,  Toshiki Yabu ,  Yoshiro Nakata ,  Naoto Matsuo ,  Shozo Okada ,  Hiroyuki Sakai

    IPC分类号： H01L21/02 ,  H01L21/8242

    CPC分类号： H01L27/10852 ,  H01L28/91

    摘要： Disclosed is a semiconductor integrating circuit having stacked capacitor cells. Each of the cells includes an electric charge storage electrode for storing an electric charge, and a capacitor insulation film and opposite plate electrode integrated thereon. The electric charge storage electrode consists essentially of a bottom and a part in at least double frame-like portion or at least one column-like portion and at least one frame-like portion surrounding the column-like portion rising upwardly from the bottom surface. The capacitor deposited film consists of a dielectric material film deposited on all of the bottom plane and all surfaces of the charge storage electrode, and constructs a capacitor in cooperation with the opposite plate electrode. The described method for making a stacked capacitor cell can make it possible to form self-aligned capacitors by repeating a deposition of an oxide film and a conductive film and an anisotropic etching.

    摘要翻译： 公开了具有层叠电容器单元的半导体积分电路。 每个单元包括用于存储电荷的电荷存储电极，以及集成在其上的电容器绝缘膜和相对的平板电极。 电荷存储电极基本上由至少双框状部分或至少一个柱状部分中的底部和部分组成，以及围绕从底面向上升起的柱状部分的至少一个框状部分。 电容器沉积膜由沉积在电荷存储电极的所有底面和所有表面上的介电材料膜构成，并与相对的板电极配合构建电容器。 所述制造叠层电容器电池的方法可以通过重复氧化膜和导电膜的沉积以及各向异性蚀刻来形成自对准电容器。