公开(公告)号：US5399890A

公开(公告)日：1995-03-21

申请号：US257955

申请日：1994-06-10

申请人： Shozo Okada ,  Hisashi Ogawa ,  Naoto Matsuo ,  Yoshiro Nakata ,  Toshiki Yabu ,  Susumu Matsumoto

发明人： Shozo Okada ,  Hisashi Ogawa ,  Naoto Matsuo ,  Yoshiro Nakata ,  Toshiki Yabu ,  Susumu Matsumoto

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/105 ,  H01L27/10808

摘要： A semiconductor memory of the invention includes a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of the plurality of transistors, a plurality of first level interconnection layers connected to other portions of the plurality of transistors, and a plurality of second level interconnection layers disposed above the stacked capacitors and the first level interconnection layers. Each of the plurality of stacked capacitors includes a first electrode layer, a capacitance insulating film formed on top of the first electrode layer, and a second electrode layer formed on top of the capacitance insulating film. The second electrode layer is connected to a portion of one of the plurality of second level interconnection layers. At least portions of the plurality of first level interconnection layers are connected to other portions of the plurality of second level interconnection layers. Each of the plurality of first level interconnection layers shares the same layer as at least one of the first electrode layer and the second electrode layer.

摘要翻译： 本发明的半导体存储器包括具有多个晶体管的半导体衬底，与多个晶体管的一部分连接的多个叠层电容器，与多个晶体管的其它部分连接的多个第一级互连层，以及多个晶体管的多个 位于层叠电容器和第一级互连层之上的第二级互连层。 多个叠层电容器中的每一个包括第一电极层，形成在第一电极层顶部的电容绝缘膜，以及形成在电容绝缘膜顶部的第二电极层。 第二电极层连接到多个第二级互连层之一的一部分。 多个第一级互连层的至少一部分连接到多个第二级互连层的其它部分。 多个第一级互连层中的每一个与第一电极层和第二电极层中的至少一个共享相同的层。

公开(公告)号：US5315543A

公开(公告)日：1994-05-24

申请号：US882064

申请日：1992-05-12

申请人： Naoto Matsuo ,  Hisashi Ogawa ,  Yoshiro Nakata ,  Shozo Okada

发明人： Naoto Matsuo ,  Hisashi Ogawa ,  Yoshiro Nakata ,  Shozo Okada

IPC分类号： H01L27/108 ,  G11C13/00

CPC分类号： H01L27/10829

摘要： A semiconductor memory device includes a single crystalline semiconductor substrate having a main surface, a plurality of active regions formed at the main surface, and an isolation region which is formed at the main surface and isolates the active regions from one another. Each of the active regions has a transistor region and a capacitor region. The capacitor region has a trench formed in the single crystalline semiconductor substrate. An inner wall of the trench is covered with an insulating layer. At least a portion of the transistor region and the insulating layer are both covered with a semiconductor layer. A portion of the semiconductor layer which covers at least the portion of the transistor region is an epitaxial layer. A portion of the semiconductor layer which covers the insulating layer is a polycrystalline layer, which functions as a storage node of a capacitor. A semiconductor memory device is manufactured by forming an isolation region for isolating a plurality of active regions from one another at a main surface of a single crystalline semiconductor substrate, forming a trench in at least a portion of the active regions of the single crystalline semiconductor substrate, covering an inner wall of the trench with an insulating layer, forming a polysilicon seed film on the insulating layer, and growing a single crystalline silicon layer and a polysilicon layer respectively on an exposed portion of the top surface of the single crystalline semiconductor substrate and on the polysilicon seed film simultaneously and selectively.

摘要翻译： 半导体存储器件包括具有主表面，形成在主表面上的多个有源区的单晶半导体衬底和形成在主表面处的隔离区，并且将有源区彼此隔离。 每个有源区具有晶体管区和电容区。 电容器区域具有在单晶半导体衬底中形成的沟槽。 沟槽的内壁被绝缘层覆盖。 晶体管区域和绝缘层的至少一部分都被半导体层覆盖。 覆盖晶体管区域的至少一部分的半导体层的一部分是外延层。 覆盖绝缘层的半导体层的一部分是用作电容器的存储节点的多晶层。 半导体存储器件通过在单晶半导体衬底的主表面上形成用于隔离多个有源区彼此的隔离区域而形成，在单晶半导体衬底的至少一部分有源区中形成沟槽 用绝缘层覆盖沟槽的内壁，在绝缘层上形成多晶硅种子膜，分别在单晶半导体衬底的顶表面的暴露部分上生长单晶硅层和多晶硅层，以及 同时和选择性地在多晶硅种子膜上。

公开(公告)号：US5242852A

公开(公告)日：1993-09-07

申请号：US944883

申请日：1992-09-11

申请人： Kazuhiro Matsuyama ,  Masanori Fukumoto ,  Yasushi Naito ,  Hisashi Ogawa ,  Shozo Okada

发明人： Kazuhiro Matsuyama ,  Masanori Fukumoto ,  Yasushi Naito ,  Hisashi Ogawa ,  Shozo Okada

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L21/768 ,  H01L28/40 ,  Y10S438/908

摘要： In a method for manufacturing DRAMs in a stacked memory cell type, an edge portion of each bit line is bared upon etching a first insulating film, the bared edge portion is etched to from an opening and an inner peripheral surface of the opening is covered by a second insulating film. There is also disclosed a method wherein second and third insulating films and second conductive film are stacked on a first insulating film, a second conductive film is formed and the second conductive film and the first conductive film are partially etched whereby the unetched portions of the first conductive film serve as electrode planes of charge storage electrodes.

摘要翻译： 在以堆叠式存储单元型制造DRAM的方法中，蚀刻第一绝缘膜时，每个位线的边缘部分被露出，裸露的边缘部分被从开口蚀刻并且开口的内周面被 第二绝缘膜。 还公开了一种方法，其中第二绝缘膜和第三绝缘膜和第二导电膜堆叠在第一绝缘膜上，形成第二导电膜，并且第二导电膜和第一导电膜被部分蚀刻，由此第一绝缘膜的未蚀刻部分 导电膜用作电荷存储电极的电极平面。

公开(公告)号：US5405800A

公开(公告)日：1995-04-11

申请号：US274048

申请日：1994-07-12

申请人： Hisashi Ogawa ,  Susumu Matsumoto ,  Shin Hashimoto ,  Hiroyuki Umimoto

发明人： Hisashi Ogawa ,  Susumu Matsumoto ,  Shin Hashimoto ,  Hiroyuki Umimoto

IPC分类号： H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10808

摘要： A method of fabricating a semiconductor memory device on a semiconductor substrate is disclosed. A gate electrode that becomes a word line, a bit line, and a charge-storage electrode are formed in a memory cell array region of a semiconductor substrate. A capacitor insulator layer and a plate electrode are formed in that order. Then, a BPSG film is formed in the memory cell array region and in the peripheral circuit region. A resist pattern is formed on the BPSG film, leaving the memory cell array region exposed. Using the resist pattern thus formed as a mask, an etching treatment is applied to remove an upper surface portion of the BPSG film lying within the memory cell array region by a given amount. After the resist pattern is removed, the BPSG film is heated in order that it reflows to planarize.

摘要翻译： 公开了一种在半导体衬底上制造半导体存储器件的方法。 在半导体衬底的存储单元阵列区域中形成成为字线，位线和电荷存储电极的栅电极。 依次形成电容器绝缘体层和平板电极。 然后，在存储单元阵列区域和外围电路区域中形成BPSG膜。 在BPSG膜上形成抗蚀剂图案，使存储单元阵列区域暴露。 使用如此形成的抗蚀剂图案作为掩模，进行蚀刻处理以将存在于存储单元阵列区域内的BPSG膜的上表面部分除去给定量。 在除去抗蚀剂图案之后，加热BPSG膜，使其回流平坦化。

公开(公告)号：US20130022819A1

公开(公告)日：2013-01-24

申请号：US13637503

申请日：2011-03-25

申请人： Yota Yano ,  Hisashi Ogawa ,  Yukio Kimoto ,  Hiroyuki Okinaka ,  Toshikatsu Suehiro ,  Mitsuo Nakamura ,  Masaru Matsuda ,  Kimio Hase

发明人： Yota Yano ,  Hisashi Ogawa ,  Yukio Kimoto ,  Hiroyuki Okinaka ,  Toshikatsu Suehiro ,  Mitsuo Nakamura ,  Masaru Matsuda ,  Kimio Hase

IPC分类号： B32B38/10 ,  B32B37/10 ,  B32B17/06

CPC分类号： B32B37/025 ,  B29C43/18 ,  B29C43/30 ,  B29C43/3697 ,  B32B2309/12

摘要： An object of the present invention is to provide a method for producing a transfer body, which method neither causes adhesion failure at the interface between a transferring film and a substrate, nor causes interlayer peeling in the transferring film. Another object of the present invention is to provide a method for producing a transfer body with high productivity, which method neither causes breakage of a functional pattern forming a transferring layer during peeling of a release film from the transferring film, nor causes any damage to the substrate during separation of an attaching roller and a peeling roller from the substrate.

摘要翻译： 本发明的目的是提供一种转印体的制造方法，该方法既不会在转印膜与基材的界面处引起粘合破坏，也不会在转印膜中产生夹层剥离。 本发明的另一个目的是提供一种高生产率的转印体的制造方法，该方法在剥离膜从转印膜剥离时不会导致形成转印层的功能图案的破损，也不会对 从基板分离粘贴辊和剥离辊时的基板。

公开(公告)号：US08258582B2

公开(公告)日：2012-09-04

申请号：US13182993

申请日：2011-07-14

申请人： Hisashi Ogawa ,  Yoshihiro Mori

发明人： Hisashi Ogawa ,  Yoshihiro Mori

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device including a first transistor of a first conductivity type provided on a first active region of a semiconductor region, and a second transistor of a second conductivity type provided on a second active region of the semiconductor region. The first transistor includes a first gate insulating film and a first gate electrode, the first gate insulating film contains a high-k material and a first metal, and the first gate electrode includes a lower conductive film, a first conductive film and a first silicon film. The second transistor includes a second gate insulating film and a second gate electrode, the second gate insulating film contains a high-k material and a second metal, and the second gate electrode includes a second conductive film made of the same material as the first conductive film, and a second silicon film.

摘要翻译： 一种半导体器件，包括设置在半导体区域的第一有源区上的第一导电类型的第一晶体管和设置在半导体区域的第二有源区上的第二导电类型的第二晶体管。 第一晶体管包括第一栅极绝缘膜和第一栅电极，第一栅极绝缘膜包含高k材料和第一金属，并且第一栅电极包括下导电膜，第一导电膜和第一硅 电影。 第二晶体管包括第二栅极绝缘膜和第二栅电极，第二栅极绝缘膜包含高k材料和第二金属，第二栅极包括由与第一导电性材料相同的材料制成的第二导电膜 膜和第二硅膜。

公开(公告)号：US20110227168A1

公开(公告)日：2011-09-22

申请号：US13149554

申请日：2011-05-31

申请人： Tsutomu Oosuka ,  Hisashi Ogawa ,  Yoshihiro Sato

发明人： Tsutomu Oosuka ,  Hisashi Ogawa ,  Yoshihiro Sato

IPC分类号： H01L29/78

CPC分类号： H01L23/535 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/11 ,  H01L29/161 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.

摘要翻译： 半导体器件包括：晶体管，其具有形成在半导体衬底上的栅极电极和形成在半导体衬底的位于栅电极两侧的部分中的第一和第二源极/漏极区域; 形成在相对于第一源极/漏极区域的与栅电极相对的位置处的栅极互连; 以及形成在所述第一源极/漏极区域上以在所述半导体衬底的顶表面上方突出的第一硅 - 锗层。 栅极互连和第一源极/漏极区域经由包括第一硅 - 锗层的局部互连结构连接。

公开(公告)号：US07872312B2

公开(公告)日：2011-01-18

申请号：US12172680

申请日：2008-07-14

申请人： Hisashi Ogawa

发明人： Hisashi Ogawa

IPC分类号： H01L29/76

CPC分类号： H01L21/823462 ,  H01L21/28202 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/665

摘要： A semiconductor device includes a first gate electrode formed in a first region on a semiconductor substrate with a first gate insulating film sandwiched therebetween; and a second gate electrode formed in a second region on the semiconductor substrate with a second gate insulating film sandwiched therebetween. The first gate insulating film includes a first high dielectric constant insulating film with a first nitrogen concentration and the second gate insulating film includes a second high dielectric constant insulating film with a second nitrogen concentration higher than the first nitrogen concentration.

摘要翻译： 半导体器件包括形成在半导体衬底上的第一区域中的第一栅电极，其间夹有第一栅极绝缘膜; 以及形成在半导体衬底上的第二区域中的第二栅极电极，其间夹有第二栅极绝缘膜。 第一栅极绝缘膜包括具有第一氮浓度的第一高介电常数绝缘膜，并且第二栅极绝缘膜包括具有高于第一氮浓度的第二氮浓度的第二高介电常数绝缘膜。

公开(公告)号：US07863753B2

公开(公告)日：2011-01-04

申请号：US11896997

申请日：2007-09-07

申请人： Chiaki Kudo ,  Hisashi Ogawa

发明人： Chiaki Kudo ,  Hisashi Ogawa

IPC分类号： H01L29/41

CPC分类号： H01L29/42376 ,  H01L21/28123 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/0207 ,  H01L29/4238

摘要： A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region; and a first gate electrode formed on the isolation region and the active region and including a first region on the isolation region. The first region has a pattern width in a gate length direction larger than a pattern width of the first gate electrode on the active region. The first region includes a part having a film thickness different from a film thickness of the first gate electrode on the active region.

摘要翻译： 半导体器件包括：形成在半导体衬底中的隔离区; 由隔离区包围的有源区; 以及形成在所述隔离区域和所述有源区域上并且包括所述隔离区域上的第一区域的第一栅电极。 第一区域具有比有源区域上的第一栅电极的图案宽度大的栅极长度方向的图案宽度。 第一区域包括具有与活性区域上的第一栅电极的膜厚度不同的膜厚度的部分。

公开(公告)号：US20100072523A1

公开(公告)日：2010-03-25

申请号：US12629508

申请日：2009-12-02

申请人： Yoshihiro SATO ,  Hisashi Ogawa

发明人： Yoshihiro SATO ,  Hisashi Ogawa

IPC分类号： H01L27/092 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate electrode includes a second metal film formed on a first gate insulating film, and an insulating film formed, extending over side surfaces of the first gate electrode and upper surfaces of regions located in the first active region laterally outside the first gate electrode. The second MIS transistor includes a second gate electrode including a first metal film formed on a second gate insulating film and a conductive film formed on the first metal film, and the insulating film formed, extending over side surfaces of the second gate electrode and upper surfaces of regions located in the second active region laterally outside the second gate electrode. The first and second metal films are made of different metal materials.

摘要翻译： 半导体器件包括第一MIS晶体管和第二MIS晶体管。 第一MIS晶体管包括：第一栅电极，包括形成在第一栅极绝缘膜上的第二金属膜和形成的绝缘膜，所述绝缘膜在第一栅电极的侧表面和位于第一有源区域的区域的上表面横向外侧延伸 第一栅电极。 第二MIS晶体管包括第二栅电极，其包括形成在第二栅极绝缘膜上的第一金属膜和形成在第一金属膜上的导电膜，并且形成在第二栅电极和上表面的侧表面上延伸的绝缘膜 位于第二有源区中的位于第二栅电极的横向外侧的区域。 第一和第二金属膜由不同的金属材料制成。