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17 条记录 (耗时 0.039 秒)

    FIXING APPARATUS, HEATING ROLLER, AND IMAGE FORMING DEVICE
    3.
    发明申请
    FIXING APPARATUS, HEATING ROLLER, AND IMAGE FORMING DEVICE 审中-公开
    固定装置，加热辊和图像形成装置

    公开(公告)号：US20090028617A1

    公开(公告)日：2009-01-29

    申请号：US11908535

    申请日：2006-03-13

    申请人： Noboru Katakabe ,  Naoto Matsuo ,  Satoru Miyanishi ,  Yasuyuki Hanada ,  Masaru Imai ,  Hideki Tatematsu ,  Shigemitsu Tani

    发明人： Noboru Katakabe ,  Naoto Matsuo ,  Satoru Miyanishi ,  Yasuyuki Hanada ,  Masaru Imai ,  Hideki Tatematsu ,  Shigemitsu Tani

    IPC分类号： G03G15/20 ,  G03G15/14

    CPC分类号： G03G15/205 ,  G03G15/2064 ,  G03G2215/2016 ,  G03G2215/2029 ,  G03G2215/2032 ,  G03G2215/2038

    摘要： There is provided a fixing apparatus capable of reducing the warm-up time, improving the heating efficiency, and suppressing the temperature increase out of the sheet width by using a magnetic adjuster. In this apparatus, the Currie temperature Tc of the magnetic adjuster material heated by electromagnetic induction is set to 220 degrees C. or below and the fixation setting temperature of a heating member corresponding to the portion where a recording material passes during continuous sheet feed is set lower than a value than the temperature at which the relative magnetic permeability of the magnetic adjuster material begins to decrease. Thus, it is possible to obtain a large difference between the heating portion and the non-heating portion, to surely prevent excessive temperature increase of the portion out of the recording material width, to reduce the warm-up time, and improve the heating efficiency.

    摘要翻译： 提供了一种定影装置，其能够通过使用磁调节器来减少预热时间，提高加热效率，并且抑制片材宽度的温度升高。 在该装置中，将通过电磁感应加热的磁调节材料的Currie温度Tc设定为220℃以下，并且设定与连续供纸期间记录材料通过的部分对应的加热部件的固定设定温度 低于磁调节材料的相对磁导率开始下降的温度的值。 因此，可以在加热部和非加热部之间获得较大的差异，可靠地防止部分超出记录材料宽度的温度升高，减少预热时间，提高加热效率 。

    Method of producing a semiconductor device having trench capacitors and vertical switching transistors
    4.
    发明授权
    Method of producing a semiconductor device having trench capacitors and vertical switching transistors 失效
    制造具有沟槽电容器和垂直开关晶体管的半导体器件的方法

    公开(公告)号：US5316962A

    公开(公告)日：1994-05-31

    申请号：US926847

    申请日：1992-08-06

    申请人： Naoto Matsuo ,  Shozo Okada ,  Michihiro Inoue

    发明人： Naoto Matsuo ,  Shozo Okada ,  Michihiro Inoue

    IPC分类号： H01L27/108 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/10841

    摘要： A semiconductor memory device is provided which includes a semiconductor substrate of a first conductivity type, a plurality of trench capacitors formed in the substrate and a plurality of switching transistors formed on the respective trench capacitors. Each of the switching transistors is electrically connected to the corresponding trench capacitor. Each of the trench capacitors has a first electrode formed in the side portion of a trench provided in the substrate and a second electrode containing impurities of the first conductivity type and embedded in the trench. Each of the switching transistors has a source region formed from a first epitaxial layer of the first conductivity type grown on the trench so as to electrically contact the second electrode, a channel region formed from a second epitaxial layer of a second conductivity type grown on the first epitaxial layer, and a drain region formed from a third epitaxial layer of the first conductivity type grown on the second epitaxial layer. The first, second and third epitaxial layers are in contact with a polycrystalline silicon layer containing impurities of the second conductivity type. The first conductivity type is opposite to the second conductivity type.

    摘要翻译： 提供了一种半导体存储器件，其包括第一导电类型的半导体衬底，形成在衬底中的多个沟槽电容器和形成在各个沟槽电容器上的多个开关晶体管。 每个开关晶体管电连接到相应的沟槽电容器。 每个沟槽电容器具有形成在设置在衬底中的沟槽的侧部中的第一电极和包含第一导电类型的杂质并且嵌入在沟槽中的第二电极。 每个开关晶体管具有由在沟槽上生长的第一导电类型的第一外延层形成的源区，以便与第二电极电接触，由第二导电类型生长的第二外延层形成的沟道区 第一外延层和由在第二外延层上生长的第一导电类型的第三外延层形成的漏极区。 第一，第二和第三外延层与含有第二导电类型杂质的多晶硅层接触。 第一导电类型与第二导电类型相反。

    Semiconductor memory device and a manufacturing method thereof
    5.
    发明授权
    Semiconductor memory device and a manufacturing method thereof 失效
    半导体存储器件及其制造方法

    公开(公告)号：US5315543A

    公开(公告)日：1994-05-24

    申请号：US882064

    申请日：1992-05-12

    申请人： Naoto Matsuo ,  Hisashi Ogawa ,  Yoshiro Nakata ,  Shozo Okada

    发明人： Naoto Matsuo ,  Hisashi Ogawa ,  Yoshiro Nakata ,  Shozo Okada

    IPC分类号： H01L27/108 ,  G11C13/00

    CPC分类号： H01L27/10829

    摘要： A semiconductor memory device includes a single crystalline semiconductor substrate having a main surface, a plurality of active regions formed at the main surface, and an isolation region which is formed at the main surface and isolates the active regions from one another. Each of the active regions has a transistor region and a capacitor region. The capacitor region has a trench formed in the single crystalline semiconductor substrate. An inner wall of the trench is covered with an insulating layer. At least a portion of the transistor region and the insulating layer are both covered with a semiconductor layer. A portion of the semiconductor layer which covers at least the portion of the transistor region is an epitaxial layer. A portion of the semiconductor layer which covers the insulating layer is a polycrystalline layer, which functions as a storage node of a capacitor. A semiconductor memory device is manufactured by forming an isolation region for isolating a plurality of active regions from one another at a main surface of a single crystalline semiconductor substrate, forming a trench in at least a portion of the active regions of the single crystalline semiconductor substrate, covering an inner wall of the trench with an insulating layer, forming a polysilicon seed film on the insulating layer, and growing a single crystalline silicon layer and a polysilicon layer respectively on an exposed portion of the top surface of the single crystalline semiconductor substrate and on the polysilicon seed film simultaneously and selectively.

    摘要翻译： 半导体存储器件包括具有主表面，形成在主表面上的多个有源区的单晶半导体衬底和形成在主表面处的隔离区，并且将有源区彼此隔离。 每个有源区具有晶体管区和电容区。 电容器区域具有在单晶半导体衬底中形成的沟槽。 沟槽的内壁被绝缘层覆盖。 晶体管区域和绝缘层的至少一部分都被半导体层覆盖。 覆盖晶体管区域的至少一部分的半导体层的一部分是外延层。 覆盖绝缘层的半导体层的一部分是用作电容器的存储节点的多晶层。 半导体存储器件通过在单晶半导体衬底的主表面上形成用于隔离多个有源区彼此的隔离区域而形成，在单晶半导体衬底的至少一部分有源区中形成沟槽 用绝缘层覆盖沟槽的内壁，在绝缘层上形成多晶硅种子膜，分别在单晶半导体衬底的顶表面的暴露部分上生长单晶硅层和多晶硅层，以及 同时和选择性地在多晶硅种子膜上。

    Semiconductor memory device and a method for producing the same
    6.
    发明授权
    Semiconductor memory device and a method for producing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US5181089A

    公开(公告)日：1993-01-19

    申请号：US731420

    申请日：1991-07-17

    申请人： Naoto Matsuo ,  Shozo Okada ,  Michihiro Inoue

    发明人： Naoto Matsuo ,  Shozo Okada ,  Michihiro Inoue

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10841

    摘要： A semiconductor memory device is provided which includes a semiconductor substrate of a first conductivity type, a plurality of trench capacitors formed in the substrate and a plurality of switching transistors formed on the respective trench capacitors. Each of the switching transistors is electrically connected to the corresponding trench capacitor. Each of the trench capacitors has a first electrode formed in the side portion of a trench provided in the substrate and a second electrode containing impurities of the first conductivity type and embedded in the trench. Each of the switching transistors has a source region formed from a first epitaxial layer of the first conductivity type grown on the trench so as to electrically contact the second electrode, a channel region formed from a second epitaxial layer of a second conductivity type grown on the first epitaxial layer, and a drain region formed from a third epitaxial layer of the first conductivity type grown on the second epitaxial layer. The first, second and third epitaxial layers are in contact with a polycrystalline silicon layer containing impurities of the second conductivity type. The first conductivity type is opposite to the second conductivity type.

    摘要翻译： 提供了一种半导体存储器件，其包括第一导电类型的半导体衬底，形成在衬底中的多个沟槽电容器和形成在各个沟槽电容器上的多个开关晶体管。 每个开关晶体管电连接到相应的沟槽电容器。 每个沟槽电容器具有形成在设置在衬底中的沟槽的侧部中的第一电极和包含第一导电类型的杂质并且嵌入在沟槽中的第二电极。 每个开关晶体管具有由在沟槽上生长的第一导电类型的第一外延层形成的源区，以便与第二电极电接触，由第二导电类型生长的第二外延层形成的沟道区 第一外延层和由在第二外延层上生长的第一导电类型的第三外延层形成的漏极区。 第一，第二和第三外延层与含有第二导电类型杂质的多晶硅层接触。 第一导电类型与第二导电类型相反。

    Heat Generating Roller, Fixing Equipment, and Image Forming Apparatus
    7.
    发明申请
    Heat Generating Roller, Fixing Equipment, and Image Forming Apparatus 有权
    发热辊，固定装置和成像装置

    公开(公告)号：US20080063445A1

    公开(公告)日：2008-03-13

    申请号：US11572521

    申请日：2005-07-25

    申请人： Masaru Imai ,  Noboru Katakabe ,  Youichi Nakamura ,  Naoto Matsuo ,  Tomoyuki Noguchi

    发明人： Masaru Imai ,  Noboru Katakabe ,  Youichi Nakamura ,  Naoto Matsuo ,  Tomoyuki Noguchi

    IPC分类号： G03G15/20

    CPC分类号： G03G15/205

    摘要： A heat generating roller, fixing equipment and an image forming apparatus in which warm-up time is shortened while preventing excessive temperature rise and good fixing performance is realized by preventing occurrence of offset. In the heat generating roller, fixing equipment and image forming apparatus, the heat generating roller is formed principally by laying a high permeability conductive layer and a nonmagnetic conductive layer in layer. When a voltage is applied from a power supply (not shown) to an exciting coil and an AC current flow through it, magnetic flux is generated around the exciting coil and a magnetic field is formed. Since the heat generating roller has the high permeability conductive layer and the nonmagnetic conductive layer laid in layer, magnetic coupling of a system consisting of the heat generating roller and the exciting coil is good at the time of low temperature and heat generation of the heat generating roller is accelerated. When the Curie point is exceeded, skin depth becomes deep and skin resistance decreases, which suppresses generation of Joule's heat and reduces heat generation of the heat generating roller.

    摘要翻译： 通过防止发生偏移来实现热发生辊，定影装置和图像形成装置，其中预热时间缩短，同时防止过高的温度升高和良好的定影性能。 在发热辊，定影设备和图像形成装置中，主要通过在层中铺设高导磁性导电层和非磁性导电层来形成发热辊。 当从电源（未示出）施加电压到励磁线圈并且AC电流流过其中时，在励磁线圈周围产生磁通并形成磁场。 由于发热辊具有高磁导率导电层和非磁性导电层，所以由发热辊和励磁线圈构成的系统的磁耦合在低温时发热良好，发热量高 滚筒加速。 当超过居里点时，皮肤深度变深并且皮肤电阻降低，这抑制了焦耳热的产生并且减少了发热辊的发热。

    Semiconductor memory device with a capacitor having a protection layer
    8.
    发明授权
    Semiconductor memory device with a capacitor having a protection layer 失效
    具有电容器的半导体存储器件具有保护层

    公开(公告)号：US5396094A

    公开(公告)日：1995-03-07

    申请号：US185768

    申请日：1994-01-24

    申请人： Naoto Matsuo

    发明人： Naoto Matsuo

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/68 ,  H01L29/78 ,  H01L29/92

    CPC分类号： H01L27/10808

    摘要： A semiconductor memory device in which a protection layer is disposed between a silicon storage electrode and a tantalum pentoxide dielectric layer. A conductive material having a larger free energy of oxide formation than that of the tantalum pentoxide is used for forming the protection layer. Therefore, no native oxide film is formed at the interface between the storage electrode and the dielectric layer. As a result, the dielectric constant of the dielectric layer does not decrease even when the dielectric layer is a thin film.

    摘要翻译： 一种半导体存储器件，其中保护层设置在硅存储电极和五氧化钽钽电介质层之间。 使用具有比五氧化二钽更大的氧化物形成自由能的导电材料来形成保护层。 因此，在存储电极和电介质层之间的界面处没有形成自然氧化膜。 结果，即使介电层是薄膜，电介质层的介电常数也不降低。

    Dram with concentric adjacent capacitors
    9.
    发明授权
    Dram with concentric adjacent capacitors 失效
    与同心相邻的电容器

    公开(公告)号：US5241201A

    公开(公告)日：1993-08-31

    申请号：US678150

    申请日：1991-04-02

    申请人： Naoto Matsuo ,  Shozo Okada ,  Susumu Matsumoto ,  Yoshiro Nakata ,  Toshiki Yabu

    发明人： Naoto Matsuo ,  Shozo Okada ,  Susumu Matsumoto ,  Yoshiro Nakata ,  Toshiki Yabu

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10817

    摘要： A new semiconductor memory device for performing a read/write of information of randomly accessed address includes a plurality of memory cells put in parallel arrays. Each memory cell includes a switching transistor region and a capacitor region. The capacitor regions of the two adjacent memory cells are formed in a common region over the switching transistor region of the two adjacent memory cells. The charge storage electrode of the capacitor region has the shape of a loop. The charge storage electrodes are formed by using self-alignment.

    摘要翻译： 用于执行随机访问地址的信息的读/写的新的半导体存储器件包括以并行阵列放置的多个存储单元。 每个存储单元包括开关晶体管区域和电容器区域。 两个相邻存储单元的电容器区域形成在两个相邻存储单元的开关晶体管区域上的公共区域中。 电容器区域的电荷存储电极具有环形。 电荷存储电极通过使用自对准形成。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5089869A

    公开(公告)日：1992-02-18

    申请号：US564087

    申请日：1990-08-07

    申请人： Naoto Matsuo ,  Shozo Okada ,  Michihiro Inoue

    发明人： Naoto Matsuo ,  Shozo Okada ,  Michihiro Inoue

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10817

    摘要： Disclosed is a semiconductor memory device comprising a semiconductor substrate on which memory cells are formed, each including a switching transistor formed on the semiconductor substrate and a capacitor disposed above the switching transistor. The capacitor has a storage electrode, a cell plate and a capacitor insulating film sandwiched therebetween. The storage electrodes of at least two adjacent memory cells are partly disposed one above the other, with part of the cell plate interposed therebetween. Also disclosed is a semiconductor memory device in which the capacitors of the memory cells are disposed in a trench formed in the semiconductor substrate. The two switching transistors of two adjacent memory cells are located on each island-shaped active region surrounded by the trench. The storage electrodes of the capacitors of the two adjacent memory cells extend side by side around the corresponding active region, with part of the cell plate interposed between the storage electrodes.

    摘要翻译： 公开了一种半导体存储器件，包括其上形成有存储单元的半导体衬底，每个半导体衬底包括形成在半导体衬底上的开关晶体管和设置在开关晶体管上方的电容器。 电容器具有夹在其间的存储电极，电池板和电容绝缘膜。 至少两个相邻的存储单元的存储电极被部分地设置在另一个之上，其中单元板的一部分插入其间。 还公开了一种半导体存储器件，其中存储单元的电容器设置在形成于半导体衬底中的沟槽中。 两个相邻存储器单元的两个开关晶体管位于由沟槽围绕的每个岛状有源区上。 两个相邻存储单元的电容器的存储电极围绕相应的有源区域并排延伸，其中一部分单元板插在存储电极之间。