公开(公告)号：US10700697B2

公开(公告)日：2020-06-30

申请号：US15998842

申请日：2018-08-17

Applicant: OLYMPUS CORPORATION

Inventor： Masato Osawa ,  Yasunari Harada ,  Shuzo Hiraide ,  Hideki Kato

IPC: H04N5/374 ,  H03M1/46 ,  H04N9/04 ,  H04N5/3745 ,  H04N5/378 ,  H03M1/12

Abstract: In an AD converter, a first DAC circuit performs a first operation in parallel with a second operation performed by a second DAC circuit, and the first DAC circuit performs the second operation in parallel with the first operation performed by the second DAC circuit. In the first operation, electric charge corresponding to an input signal of the first DAC circuit or an input signal of the second DAC circuit is sampled. In the second operation, an AD conversion is sequentially performed on the basis of the electric charge sampled in the first operation. The first DAC circuit and the second DAC circuit alternately perform the first operation and the second operation.

公开(公告)号：US10601436B2

公开(公告)日：2020-03-24

申请号：US16415067

申请日：2019-05-17

Applicant: OLYMPUS CORPORATION

Inventor： Shuzo Hiraide ,  Yasunari Harada ,  Masato Osawa

IPC: H03M1/34 ,  H03M1/38 ,  A61B1/045 ,  H04N5/378 ,  H03M1/10 ,  H03M1/80

Abstract: A disclosed analog-to-digital converter includes; a sampling circuit to sample a pair of analog signals as a differential input signal; a binary capacitance holding the sampled pair of analog signals and reflecting a level of a reference signal to the analog signals through the binary capacitance to generate a pair of voltage signals; a comparator including a transistor to which the voltage signals are input, to compare one of the voltage signals with the other; a correction circuit provided previously to the comparator, to output to the comparator the pair of voltage signals in which voltage dependency of stray capacitance in the input transistor is cancelled; and a controller that successively determines a value of each bit of a digital signal corresponding to the binary capacitance based on a comparison by the comparison circuit, and reflects the value of each bit of the digital signal to the reference signal.

公开(公告)号：US10516410B2

公开(公告)日：2019-12-24

申请号：US16100534

申请日：2018-08-10

Applicant: OLYMPUS CORPORATION

Inventor： Shuzo Hiraide ,  Yasunari Harada ,  Masato Osawa ,  Hideki Kato

IPC: H03M1/46 ,  H01G4/012 ,  H01L23/522 ,  H01G4/38 ,  H01G4/40

Abstract: An A/D converter includes: a first wiring layer including a first A/D conversion circuit including a first capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a second capacitor group in which a plurality of unit capacitors are connected in parallel, the second capacitor group being connected in parallel with the first capacitor group; and a second wiring layer including a second A/D conversion circuit including a third capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a fourth capacitor group in which a plurality of unit capacitors are connected in parallel, the fourth capacitor group being connected in parallel with the third capacitor group, in which the first wiring layer and the second wiring layer are stacked such that the first A/D conversion circuit and the second A/D conversion circuit are disposed at overlapping positions.

公开(公告)号：US10277237B2

公开(公告)日：2019-04-30

申请号：US16043920

申请日：2018-07-24

Applicant: OLYMPUS CORPORATION

Inventor： Yasunari Harada ,  Shuzo Hiraide ,  Masato Osawa ,  Hideki Kato

IPC: H03M1/38 ,  H03M1/00 ,  H03M1/74 ,  H03M1/12 ,  H03M1/10

Abstract: A successive approximation type A/D conversion circuit includes a first capacitor circuit, a second capacitor circuit, a plurality of comparison circuits, a determination circuit, and a control circuit. The determination circuit counts a first number of first state and a second number of second state with respect to a plurality of first digital signals output from the plurality of comparison circuits. The determination circuit outputs a control signal for stopping the plurality of comparison circuits to the control circuit when an absolute value of a difference between the first number and the second number is equal to or smaller than 1. The control circuit stops the plurality of comparison circuits on the basis of the control signal.

公开(公告)号：US20180351568A1

公开(公告)日：2018-12-06

申请号：US16100534

申请日：2018-08-10

Applicant: OLYMPUS CORPORATION

Inventor： Shuzo Hiraide ,  Yasunari Harada ,  Masato Osawa ,  Hideki Kato

IPC: H03M1/46 ,  H01G4/012 ,  H01G4/38 ,  H01L23/522

CPC classification number: H03M1/46 ,  H01G4/012 ,  H01G4/38 ,  H01G4/40 ,  H01L23/5223 ,  H01L23/5225 ,  H03M1/466

Abstract: An A/D converter includes: a first wiring layer including a first A/D conversion circuit including a first capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a second capacitor group in which a plurality of unit capacitors are connected in parallel, the second capacitor group being connected in parallel with the first capacitor group; and a second wiring layer including a second A/D conversion circuit including a third capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a fourth capacitor group in which a plurality of unit capacitors are connected in parallel, the fourth capacitor group being connected in parallel with the third capacitor group, in which the first wiring layer and the second wiring layer are stacked such that the first A/D conversion circuit and the second A/D conversion circuit are disposed at overlapping positions.

公开(公告)号：US10090851B2

公开(公告)日：2018-10-02

申请号：US15814955

申请日：2017-11-16

Applicant: OLYMPUS CORPORATION

Inventor： Shuzo Hiraide

IPC: H03M1/00 ,  H03M1/38 ,  H03M1/10 ,  H01G4/002 ,  H03M1/26

Abstract: A sampling circuit in a successive approximation type analog-to-digital (A/D) converting device samples a pair of analog signals constituting a differential input signal. A capacitor circuit reflects a signal level of a reference signal in the pair of analog signals through an attenuation capacitance unit and a binary capacitance unit to generate a pair of voltage signals. A comparison circuit compares the pair of voltage signals. A control circuit determines a value of each bit of a digital signal on the basis of the result of the comparison and reflects the value in the reference signal. The attenuation capacitance unit includes a fixed capacitance unit connected between a signal node at which the sampled analog signals are held and a predetermined potential node and a variable capacitance unit connected between the signal node and the predetermined potential node in parallel with the fixed capacitance unit.