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公开(公告)号：US11736092B2
公开(公告)日：2023-08-22
申请号：US17893832
申请日：2022-08-23
Applicant: OLYMPUS CORPORATION
Inventor： Takanori Tanaka , Shuzo Hiraide
CPC classification number: H03H11/16 , H03L7/0814 , G11C7/222
Abstract: In a phase adjustment circuit, a binary circuit is configured to output a binary signal on the basis of an edge of a video signal. A phase-delayed clock signal generation circuit is configured to generate a phase-delayed clock signal having a later phase than a phase of a clock signal by a first delay amount. A delay time control circuit is configured to cause a phase of the binary signal and the phase of the phase-delayed clock signal to match each other by adjusting the first delay amount. A sampling signal generation circuit is configured to generate a sampling signal having a later phase than the phase of the clock signal by a second delay amount. The second delay amount is in accordance with both a phase shift amount, which is based on the clock signal, and the first delay amount.
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公开(公告)号：US20180358977A1
公开(公告)日：2018-12-13
申请号：US16106687
申请日：2018-08-21
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato , Yasunari Harada , Shuzo Hiraide , Masato Osawa
IPC: H03M1/46
Abstract: In an AD converter, a first capacitor DAC circuit performs a first operation in parallel with a second operation by a second capacitor DAC circuit, and the first capacitor DAC circuit performs the second operation in parallel with the first operation by the second capacitor DAC circuit. Electric charge corresponding to an input signal is sampled in the first operation. AD conversions are sequentially performed on the basis of the electric charge sampled in each first capacitor included in a plurality of first capacitors or each second capacitor included in a plurality of second capacitors in the second operation. The first capacitor DAC circuit and the second capacitor DAC circuit alternately perform the first operation and the second operation.
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公开(公告)号：US20180331688A1
公开(公告)日：2018-11-15
申请号：US16043920
申请日：2018-07-24
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada , Shuzo Hiraide , Masato Osawa , Hideki Kato
IPC: H03M1/00
CPC classification number: H03M1/002 , H03M1/00 , H03M1/001 , H03M1/10 , H03M1/12 , H03M1/38 , H03M1/74
Abstract: A successive approximation type A/D conversion circuit includes a first capacitor circuit, a second capacitor circuit, a plurality of comparison circuits, a determination circuit, and a control circuit. The determination circuit counts a first number of first state and a second number of second state with respect to a plurality of first digital signals output from the plurality of comparison circuits. The determination circuit outputs a control signal for stopping the plurality of comparison circuits to the control circuit when an absolute value of a difference between the first number and the second number is equal to or smaller than 1. The control circuit stops the plurality of comparison circuits on the basis of the control signal.
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公开(公告)号：US20180083646A1
公开(公告)日：2018-03-22
申请号：US15814955
申请日：2017-11-16
Applicant: OLYMPUS CORPORATION
Inventor： Shuzo Hiraide
CPC classification number: H03M1/38 , H01G4/002 , H01G4/38 , H01G4/40 , H01G5/16 , H03M1/1004 , H03M1/1061 , H03M1/1095 , H03M1/26 , H03M1/468
Abstract: A sampling circuit in a successive approximation type analog-to-digital (A/D) converting device samples a pair of analog signals constituting a differential input signal. A capacitor circuit reflects a signal level of a reference signal in the pair of analog signals through an attenuation capacitance unit and a binary capacitance unit to generate a pair of voltage signals. A comparison circuit compares the pair of voltage signals. A control circuit determines a value of each bit of a digital signal on the basis of the result of the comparison and reflects the value in the reference signal. The attenuation capacitance unit includes a fixed capacitance unit connected between a signal node at which the sampled analog signals are held and a predetermined potential node and a variable capacitance unit connected between the signal node and the predetermined potential node in parallel with the fixed capacitance unit.
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公开(公告)号：US20160345810A1
公开(公告)日：2016-12-01
申请号：US15236959
申请日：2016-08-15
Applicant: OLYMPUS CORPORATION
Inventor： Shuzo Hiraide
CPC classification number: A61B1/041 , A61B1/00006 , A61B1/00009 , A61B1/0011 , A61B1/005 , A61B1/051 , A61B1/0684 , H04N5/2256
Abstract: A capsule endoscope includes a flexible substrate which is integrally formed by disposing an illumination substrate section, a first wiring substrate section, an imaging element substrate, a second wiring substrate section, and a signal-processing substrate section in a row in sequence and an illumination control circuit which includes an illumination control signal output unit and an illumination driving unit, wherein the light-emitting elements are LEDs, wherein the illumination driving unit is disposed on the imaging element substrate section or the illumination substrate section, and wherein the illumination driving unit includes a transistor array which is formed by a plurality of transistors, the plurality of transistors corresponding to each of the light-emitting elements provided in the illumination unit and generating illumination currents in accordance with the illumination control signal.
Abstract translation: 胶囊型内窥镜包括柔性基板，其通过依次配置照明基板部分，第一布线基板部分，成像元件基板，第二布线基板部分和信号处理基板部分而一体地形成，并且照明 控制电路，其包括照明控制信号输出单元和照明驱动单元，其中所述发光元件是LED，其中所述照明驱动单元设置在所述摄像元件基板部分或照明基板部分上，并且其中所述照明驱动单元 包括由多个晶体管形成的晶体管阵列，所述多个晶体管对应于设置在照明单元中的每个发光元件，并根据照明控制信号产生照明电流。
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Patent Agency Ranking
公开(公告)号：US20180367160A1
公开(公告)日：2018-12-20
申请号：US15998842
申请日：2018-08-17
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa , Yasunari Harada , Shuzo Hiraide , Hideki Kato
IPC: H03M1/46 , H04N5/378 , H04N9/04 , H04N5/3745
CPC classification number: H03M1/466 , H03M1/123 , H03M1/468 , H04N5/3742 , H04N5/37455 , H04N5/378 , H04N9/0455
Abstract: In an AD converter, a first DAC circuit performs a first operation in parallel with a second operation performed by a second DAC circuit, and the first DAC circuit performs the second operation in parallel with the first operation performed by the second DAC circuit. In the first operation, electric charge corresponding to an input signal of the first DAC circuit or an input signal of the second DAC circuit is sampled. In the second operation, an AD conversion is sequentially performed on the basis of the electric charge sampled in the first operation. The first DAC circuit and the second DAC circuit alternately perform the first operation and the second operation.
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公开(公告)号：US20220407501A1
公开(公告)日：2022-12-22
申请号：US17893832
申请日：2022-08-23
Applicant: OLYMPUS CORPORATION
Inventor： Takanori Tanaka , Shuzo Hiraide
Abstract: In a phase adjustment circuit, a binary circuit is configured to output a binary signal on the basis of an edge of a video signal. A phase-delayed clock signal generation circuit is configured to generate a phase-delayed clock signal having a later phase than a phase of a clock signal by a first delay amount. A delay time control circuit is configured to cause a phase of the binary signal and the phase of the phase-delayed clock signal to match each other by adjusting the first delay amount. A sampling signal generation circuit is configured to generate a sampling signal having a later phase than the phase of the clock signal by a second delay amount. The second delay amount is in accordance with both a phase shift amount, which is based on the clock signal, and the first delay amount.
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公开(公告)号：US10812099B2
公开(公告)日：2020-10-20
申请号：US16106687
申请日：2018-08-21
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato , Yasunari Harada , Shuzo Hiraide , Masato Osawa
Abstract: In an AD converter, a first capacitor DAC circuit performs a first operation in parallel with a second operation by a second capacitor DAC circuit, and the first capacitor DAC circuit performs the second operation in parallel with the first operation by the second capacitor DAC circuit. Electric charge corresponding to an input signal is sampled in the first operation. AD conversions are sequentially performed on the basis of the electric charge sampled in each first capacitor included in a plurality of first capacitors or each second capacitor included in a plurality of second capacitors in the second operation. The first capacitor DAC circuit and the second capacitor DAC circuit alternately perform the first operation and the second operation.
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公开(公告)号：US10757357B2
公开(公告)日：2020-08-25
申请号：US16442666
申请日：2019-06-17
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada , Shuzo Hiraide , Masato Osawa , Satoru Adachi
Abstract: An imaging element includes: a plurality of pixels where each pixel is configured to generate an imaging signal; a noise eliminating circuit configured to eliminate a noise component included in the imaging signal; a plurality of column source follower buffers where each column source follower buffer is configured to amplify the imaging signal from which the noise component has been eliminated by the noise eliminating circuit, and output the amplified signal; a horizontal scanning circuit configured to sequentially select the column source follower buffer and output the imaging signal; and a buffer circuit which is connected with the column source follower buffer sequentially selected by the horizontal scanning circuit to form a voltage follower circuit, the buffer circuit being configured to perform impedance conversion on a voltage of the imaging signal output from the column source follower buffer, and output the converted signal to an outside.
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10.发明授权公开(公告)号：US10172512B2
公开(公告)日：2019-01-08
申请号：US15236959
申请日：2016-08-15
Applicant: OLYMPUS CORPORATION
Inventor： Shuzo Hiraide
Abstract: A capsule endoscope includes a flexible substrate which is integrally formed by disposing an illumination substrate section, a first wiring substrate section, an imaging element substrate, a second wiring substrate section, and a signal-processing substrate section in a row in sequence and an illumination control circuit which includes an illumination control signal output unit and an illumination driving unit, wherein the light-emitting elements are LEDs, wherein the illumination driving unit is disposed on the imaging element substrate section or the illumination substrate section, and wherein the illumination driving unit includes a transistor array which is formed by a plurality of transistors, the plurality of transistors corresponding to each of the light-emitting elements provided in the illumination unit and generating illumination currents in accordance with the illumination control signal.
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