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公开(公告)号：US10812099B2
公开(公告)日：2020-10-20
申请号：US16106687
申请日：2018-08-21
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato , Yasunari Harada , Shuzo Hiraide , Masato Osawa
Abstract: In an AD converter, a first capacitor DAC circuit performs a first operation in parallel with a second operation by a second capacitor DAC circuit, and the first capacitor DAC circuit performs the second operation in parallel with the first operation by the second capacitor DAC circuit. Electric charge corresponding to an input signal is sampled in the first operation. AD conversions are sequentially performed on the basis of the electric charge sampled in each first capacitor included in a plurality of first capacitors or each second capacitor included in a plurality of second capacitors in the second operation. The first capacitor DAC circuit and the second capacitor DAC circuit alternately perform the first operation and the second operation.
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公开(公告)号：US20190350447A1
公开(公告)日：2019-11-21
申请号：US16525880
申请日：2019-07-30
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato
Abstract: In a solid-state imaging device, a power supply voltage is input to a power supply terminal. A power supply line connects together the power supply terminal and a first control circuit. A detection circuit detects the power supply voltage input to the power supply terminal and a first digital signal corresponding to the detected power supply voltage. An output terminal outputs the first digital signal output from the detection circuit and a second digital signal corresponding to pixel signals.
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公开(公告)号：US10277845B2
公开(公告)日：2019-04-30
申请号：US15902014
申请日：2018-02-22
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato , Yasunari Harada , Masato Osawa
Abstract: There is provided a method of driving a solid-state imaging device, the solid-state imaging device including a plurality of column circuits which are arranged for each column of pixels and an amplification and selection circuit configured to amplify a differential signal based on a column pixel signal and a column reset signal, the method including causing the amplification and selection circuit to perform at least two operations among a first operation of sampling the column pixel signal, a second operation of sampling the column reset signal, and a third operation of output the amplified differential signal in parallel in the same period; and causing components connected to different horizontal signal lines to perform operations corresponding to the first to third operation in that order, and causing the components to perform different operations in parallel in the same period with respect to the first to third operations.
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公开(公告)号：US20180062595A1
公开(公告)日：2018-03-01
申请号：US15788505
申请日：2017-10-19
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa , Yasunari Harada , Hideki Kato
CPC classification number: H03F3/72 , H03F1/26 , H03F3/45475 , H03F2200/135 , H03F2200/213 , H03F2200/411 , H03F2200/45 , H03F2203/45514 , H03F2203/45551 , H03F2203/7231 , H03G1/0094 , H03G3/001 , H03M1/1245
Abstract: In a semiconductor device, a first variable gain amplifier and a second variable gain amplifier constitute a switched capacitor type variable gain amplifier. A selection switch switches connection among the first variable gain amplifier, the second variable gain amplifier, and a load circuit such that the first variable gain amplifier and the load circuit are connected to each other when an amplification factor of the first variable gain amplifier is a predetermined gain or less, and the second variable gain amplifier is connected between the first variable gain amplifier and the load circuit when the amplification factor of the first variable gain amplifier is larger than the predetermined gain.
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公开(公告)号：US20140139713A1
公开(公告)日：2014-05-22
申请号：US13683687
申请日：2012-11-21
Applicant: OLYMPUS CORPORATION
Inventor： Yuichi Gomi , Hideki Kato , Naofumi Sakaguchi , Naoto Fukuoka
IPC: H04N5/335
CPC classification number: H04N5/378 , H01L24/14 , H01L27/14618 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H04N5/345 , H04N5/353 , H04N5/3598 , H04N5/363 , H04N5/3698 , H04N5/37457 , H01L2924/00
Abstract: This solid-state imaging device includes a first substrate and a second substrate which have circuit elements constituting pixels disposed therein are electrically connected to each other. The pixels includes: a photoelectric conversion element disposed in the first substrate; an amplifier circuit that amplifies a signal generated in the photoelectric conversion element to output the amplified signal; a signal accumulation circuit which is disposed in the second substrate and accumulates the amplified signal which is output from the amplifier circuit; and an output circuit that outputs the amplified signal accumulated in the signal accumulation circuit from the pixel.
Abstract translation: 该固态成像装置包括第一基板和第二基板，其中构成像素的电路元件彼此电连接。 像素包括：设置在第一基板中的光电转换元件; 放大电路，放大在所述光电转换元件中产生的信号，以输出放大的信号; 信号累积电路，其设置在所述第二基板中，并累加从所述放大电路输出的放大信号; 以及输出电路，其从像素输出累积在信号累积电路中的放大信号。
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Patent Agency Ranking
公开(公告)号：US20130250151A1
公开(公告)日：2013-09-26
申请号：US13838838
申请日：2013-03-15
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato
IPC: H04N5/335
CPC classification number: H04N5/335 , H04N5/3745 , H04N5/37452
Abstract: In a solid-state imaging device, an amplification transistor amplifies a signal generated by a photoelectric conversion unit and outputs the amplified signal. An analog memory accumulates the amplified signal output from the amplification transistor. A select transistor electrically connects the analog memory to a vertical signal line and selects any one of a first state in which the amplified signal accumulated in the analog memory is output to the vertical signal line and a second state in which the analog memory is electrically disconnected from the vertical signal line. A differential amplification circuit includes a first input terminal connected to a reference voltage and a second input terminal connected to the vertical signal line.
Abstract translation: 在固态成像装置中，放大晶体管放大由光电转换单元生成的信号，并输出放大的信号。 模拟存储器累积从放大晶体管输出的放大信号。 选择晶体管将模拟存储器电连接到垂直信号线，并且选择其中累积在模拟存储器中的放大信号被输出到垂直信号线的第一状态中的任何一个以及模拟存储器电断开的第二状态 从垂直信号线。 差分放大电路包括连接到参考电压的第一输入端和连接到垂直信号线的第二输入端。
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公开(公告)号：US11516420B2
公开(公告)日：2022-11-29
申请号：US17038291
申请日：2020-09-30
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato
Abstract: An imaging system includes a camera unit and a main body. A clock detection circuit is configured to detect a first clock signal of the camera unit from first digital data transmitted from the camera unit. A phase comparator is configured to generate second digital data that represent a difference between a phase of the first clock signal and a phase of a second clock signal of the main body. A second communicator is configured to perform communication in a second direction in which the second digital data are transmitted to the camera unit in a blanking period. A first clock generation circuit is configured to generate the first clock signal synchronized with the second clock signal on the basis of the second digital data.
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公开(公告)号：US10925473B2
公开(公告)日：2021-02-23
申请号：US16525880
申请日：2019-07-30
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato
Abstract: In a solid-state imaging device, a power supply voltage is input to a power supply terminal. A power supply line connects together the power supply terminal and a first control circuit. A detection circuit detects the power supply voltage input to the power supply terminal and a first digital signal corresponding to the detected power supply voltage. An output terminal outputs the first digital signal output from the detection circuit and a second digital signal corresponding to pixel signals.
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公开(公告)号：US10298216B2
公开(公告)日：2019-05-21
申请号：US15837299
申请日：2017-12-11
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada , Masato Osawa , Hideki Kato
Abstract: A semiconductor device is provided that includes an amplification circuit, a downstream circuit, and a clipping circuit. The amplification circuit includes a sampling capacitor, a feedback capacitor, and an operational amplifier circuit. The sampling capacitor holds air input signal on which sampling is performed, as a signal whose reference is a first reference voltage. The signal that is held in the sampling capacitor is transferred to the feedback capacitor. The operational amplifier circuit amplifies the signal that is held in the sampling capacitor, according to a ratio between values of the sampling capacitor and the feedback capacitor, and outputs the amplified signal, as a signal whose reference is a second reference voltage. The clipping circuit limits a voltage of an output signal of the operational amplifier circuit to a predetermined voltage or below.
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公开(公告)号：US20180367160A1
公开(公告)日：2018-12-20
申请号：US15998842
申请日：2018-08-17
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa , Yasunari Harada , Shuzo Hiraide , Hideki Kato
IPC: H03M1/46 , H04N5/378 , H04N9/04 , H04N5/3745
CPC classification number: H03M1/466 , H03M1/123 , H03M1/468 , H04N5/3742 , H04N5/37455 , H04N5/378 , H04N9/0455
Abstract: In an AD converter, a first DAC circuit performs a first operation in parallel with a second operation performed by a second DAC circuit, and the first DAC circuit performs the second operation in parallel with the first operation performed by the second DAC circuit. In the first operation, electric charge corresponding to an input signal of the first DAC circuit or an input signal of the second DAC circuit is sampled. In the second operation, an AD conversion is sequentially performed on the basis of the electric charge sampled in the first operation. The first DAC circuit and the second DAC circuit alternately perform the first operation and the second operation.
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