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公开(公告)号：US11206377B2
公开(公告)日：2021-12-21
申请号：US17105826
申请日：2020-11-27
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada , Satoru Adachi
Abstract: An imaging apparatus includes: an imager configured to generate an imaging signal; a transmission channel configured to connect a controller and the images; a superimposed signal generator that is arranged on a proximal end side of the transmission channel, the superimposed signal generator being configured to generate a superimposed signal by superimposing a pulsed data signal and a pulsed reference clock signal, and output the generated superimposed signal to the transmission channel; a first extractor that is arranged on a distal end side of the transmission channel, the first extractor being configured to extract the data signal and the reference clock signal from the generated superimposed signal; and a second extractor that is arranged on the distal end side of the transmission channel, the second extractor being configured to extract the negative voltage from the generated superimposed signal.
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公开(公告)号：US20180331688A1
公开(公告)日：2018-11-15
申请号：US16043920
申请日：2018-07-24
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada , Shuzo Hiraide , Masato Osawa , Hideki Kato
IPC: H03M1/00
CPC classification number: H03M1/002 , H03M1/00 , H03M1/001 , H03M1/10 , H03M1/12 , H03M1/38 , H03M1/74
Abstract: A successive approximation type A/D conversion circuit includes a first capacitor circuit, a second capacitor circuit, a plurality of comparison circuits, a determination circuit, and a control circuit. The determination circuit counts a first number of first state and a second number of second state with respect to a plurality of first digital signals output from the plurality of comparison circuits. The determination circuit outputs a control signal for stopping the plurality of comparison circuits to the control circuit when an absolute value of a difference between the first number and the second number is equal to or smaller than 1. The control circuit stops the plurality of comparison circuits on the basis of the control signal.
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公开(公告)号：US10298216B2
公开(公告)日：2019-05-21
申请号：US15837299
申请日：2017-12-11
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada , Masato Osawa , Hideki Kato
Abstract: A semiconductor device is provided that includes an amplification circuit, a downstream circuit, and a clipping circuit. The amplification circuit includes a sampling capacitor, a feedback capacitor, and an operational amplifier circuit. The sampling capacitor holds air input signal on which sampling is performed, as a signal whose reference is a first reference voltage. The signal that is held in the sampling capacitor is transferred to the feedback capacitor. The operational amplifier circuit amplifies the signal that is held in the sampling capacitor, according to a ratio between values of the sampling capacitor and the feedback capacitor, and outputs the amplified signal, as a signal whose reference is a second reference voltage. The clipping circuit limits a voltage of an output signal of the operational amplifier circuit to a predetermined voltage or below.
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公开(公告)号：US20180367160A1
公开(公告)日：2018-12-20
申请号：US15998842
申请日：2018-08-17
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa , Yasunari Harada , Shuzo Hiraide , Hideki Kato
IPC: H03M1/46 , H04N5/378 , H04N9/04 , H04N5/3745
CPC classification number: H03M1/466 , H03M1/123 , H03M1/468 , H04N5/3742 , H04N5/37455 , H04N5/378 , H04N9/0455
Abstract: In an AD converter, a first DAC circuit performs a first operation in parallel with a second operation performed by a second DAC circuit, and the first DAC circuit performs the second operation in parallel with the first operation performed by the second DAC circuit. In the first operation, electric charge corresponding to an input signal of the first DAC circuit or an input signal of the second DAC circuit is sampled. In the second operation, an AD conversion is sequentially performed on the basis of the electric charge sampled in the first operation. The first DAC circuit and the second DAC circuit alternately perform the first operation and the second operation.
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公开(公告)号：US20220322923A1
公开(公告)日：2022-10-13
申请号：US17852503
申请日：2022-06-29
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada
Abstract: In an imaging system, a video output circuit is configured to convert an analog video signal into digital data and output serial data including the digital data to a signal line on the basis of a serial clock having a higher frequency than a frequency of the camera clock. A camera-clock generation circuit is configured to generate the camera clock synchronized with the system clock output to the signal line. A serial-clock generation circuit is configured to generate the serial clock synchronized with the system clock output to the signal line. A system-clock output circuit is configured to output the system clock to the signal line in a blanking period.
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Patent Agency Ranking
公开(公告)号：US20180358977A1
公开(公告)日：2018-12-13
申请号：US16106687
申请日：2018-08-21
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato , Yasunari Harada , Shuzo Hiraide , Masato Osawa
IPC: H03M1/46
Abstract: In an AD converter, a first capacitor DAC circuit performs a first operation in parallel with a second operation by a second capacitor DAC circuit, and the first capacitor DAC circuit performs the second operation in parallel with the first operation by the second capacitor DAC circuit. Electric charge corresponding to an input signal is sampled in the first operation. AD conversions are sequentially performed on the basis of the electric charge sampled in each first capacitor included in a plurality of first capacitors or each second capacitor included in a plurality of second capacitors in the second operation. The first capacitor DAC circuit and the second capacitor DAC circuit alternately perform the first operation and the second operation.
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公开(公告)号：US09979364B2
公开(公告)日：2018-05-22
申请号：US15788505
申请日：2017-10-19
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa , Yasunari Harada , Hideki Kato
CPC classification number: H03F3/72 , H03F1/26 , H03F3/45475 , H03F2200/135 , H03F2200/213 , H03F2200/411 , H03F2200/45 , H03F2203/45514 , H03F2203/45551 , H03F2203/7231 , H03G1/0094 , H03G3/001 , H03M1/1245
Abstract: In a semiconductor device, a first variable gain amplifier and a second variable gain amplifier constitute a switched capacitor type variable gain amplifier. A selection switch switches connection among the first variable gain amplifier, the second variable gain amplifier, and a load circuit such that the first variable gain amplifier and the load circuit are connected to each other when an amplification factor of the first variable gain amplifier is a predetermined gain or less, and the second variable gain amplifier is connected between the first variable gain amplifier and the load circuit when the amplification factor of the first variable gain amplifier is larger than the predetermined gain.
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公开(公告)号：US09362873B2
公开(公告)日：2016-06-07
申请号：US14810853
申请日：2015-07-28
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada
IPC: H03F3/45
CPC classification number: H03F3/45179 , H03F3/45197 , H03F2200/261 , H03F2203/45026
Abstract: An instrumentation amplifier includes: a first input stage configured to shift a level of a first input voltage applied to a first input terminal and to output the level-shifted voltage; a second input stage configured to shift a level of a second input voltage applied to a second input terminal and to output the level-shifted voltage; a first resistor configured to generate a differential current corresponding to a difference between the voltage output from the first input stage and the voltage output from the second input stage; a second resistor configured to convert the differential current into a first output voltage; a third resistor configured to convert the differential current into a second output voltage; a first output stage configured to output the first output voltage from a first output terminal; and a second output stage configured to output the second output voltage from a second output terminal.
Abstract translation: 仪表放大器包括：第一输入级，被配置为移位施加到第一输入端的第一输入电压的电平并输出电平移位电压; 第二输入级，被配置为移位施加到第二输入端的第二输入电压的电平并输出电平移位电压; 第一电阻器，被配置为产生对应于从第一输入级输出的电压与从第二输入级输出的电压之间的差的差分电流; 第二电阻器，被配置为将所述差分电流转换为第一输出电压; 第三电阻器，被配置为将所述差分电流转换为第二输出电压; 第一输出级，被配置为从第一输出端子输出第一输出电压; 以及第二输出级，被配置为从第二输出端子输出第二输出电压。
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公开(公告)号：US12213651B2
公开(公告)日：2025-02-04
申请号：US17852503
申请日：2022-06-29
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada
Abstract: In an imaging system, a video output circuit is configured to convert an analog video signal into digital data and output serial data including the digital data to a signal line on the basis of a serial clock having a higher frequency than a frequency of the camera clock. A camera-clock generation circuit is configured to generate the camera clock synchronized with the system clock output to the signal line. A serial-clock generation circuit is configured to generate the serial clock synchronized with the system clock output to the signal line. A system-clock output circuit is configured to output the system clock to the signal line in a blanking period.
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公开(公告)号：US10812099B2
公开(公告)日：2020-10-20
申请号：US16106687
申请日：2018-08-21
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato , Yasunari Harada , Shuzo Hiraide , Masato Osawa
Abstract: In an AD converter, a first capacitor DAC circuit performs a first operation in parallel with a second operation by a second capacitor DAC circuit, and the first capacitor DAC circuit performs the second operation in parallel with the first operation by the second capacitor DAC circuit. Electric charge corresponding to an input signal is sampled in the first operation. AD conversions are sequentially performed on the basis of the electric charge sampled in each first capacitor included in a plurality of first capacitors or each second capacitor included in a plurality of second capacitors in the second operation. The first capacitor DAC circuit and the second capacitor DAC circuit alternately perform the first operation and the second operation.
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