公开(公告)号：US12262562B2

公开(公告)日：2025-03-25

申请号：US17463222

申请日：2021-08-31

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Seong Yeol Mun

IPC: H10F39/18 ,  H10F39/00 ,  H10F39/12

Abstract: An image sensor comprises a first photodiode, a second photodiode, and a deep trench isolation structure. The first photodiode and the second photodiode are each disposed within a semiconductor substrate. The first photodiode is adjacent to the second photodiode. The deep trench isolation structure has a varying depth disposed within the semiconductor substrate between the first photodiode and the second photodiode. The DTI structure extends the varying depth from a first side of the semiconductor substrate towards a second side of the semiconductor substrate. The first side of the semiconductor substrate is opposite of the second side of the semiconductor substrate.

公开(公告)号：US12107107B2

公开(公告)日：2024-10-01

申请号：US17530296

申请日：2021-11-18

Applicant: OmniVision Technologies, Inc.

Inventor： Yifei Du ,  Zhiqiang Lin ,  Hui Zang ,  Seong Yeol Mun

IPC: H01L27/14 ,  H01L27/146

CPC classification number: H01L27/14632 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14645

Abstract: A dark-current-inhibiting image sensor includes a semiconductor substrate, a thin and a thin junction. The semiconductor substrate includes a front surface, a back surface opposite the front surface, a photodiode, and a concave surface between the front surface and the back surface. The concave surface extends from the back surface toward the front surface, and defines a trench that surrounds the photodiode in a cross-sectional plane parallel to the back surface. The thin junction extends from the concave surface into the semiconductor substrate, and is a region of the semiconductor substrate. The semiconductor substrate includes a first substrate region, located between the thin junction and the photodiode, that has a first conductive type. The photodiode and the thin junction have a second conductive type opposite the first conductive type.

公开(公告)号：US11862509B2

公开(公告)日：2024-01-02

申请号：US17319368

申请日：2021-05-13

Applicant: OmniVision Technologies, Inc.

Inventor： Seong Yeol Mun ,  Heesoo Kang ,  Xiang Zhang

IPC: H01L27/146 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689

Abstract: A shallow trench isolation (STI) structure and method of fabrication includes forming a shallow trench isolation (STI) structure having a polygonal shaped cross-section in a semiconductor substrate of an image sensor includes a two-step etching process. The first step is a dry plasma etch that forms a portion of the trench to a first depth. The second step is a wet etch process that completes the trench etching to the desired depth and cures damage caused by the dry etch process. A CMOS image sensor includes a semiconductor substrate having a photodiode region and a pixel transistor region separated by a shallow trench isolation (STI) structure having a polygonal shaped cross-section.

公开(公告)号：US20210358993A1

公开(公告)日：2021-11-18

申请号：US16877077

申请日：2020-05-18

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Duli Mao ,  Bill Phan ,  Keiji Mabuchi ,  Seong Yeol Mun ,  Yuanliang Liu ,  Vincent Venezia

IPC: H01L27/146 ,  H04N5/378 ,  H04N5/355

Abstract: A pixel cell includes a plurality of subpixels to generate image charge in response to incident light. The subpixels include an inner subpixel laterally surrounded by outer subpixels. A first plurality of transfer gates disposed proximate to the inner subpixel and a first grouping of outer subpixels. A first floating diffusion is coupled to receive the image charge from the first grouping of outer subpixels through a first plurality of transfer gates. A second plurality of transfer gates disposed proximate to the inner subpixel and the second grouping of outer subpixels. A second floating diffusion disposed in the semiconductor material and coupled to receive the image charge from each one of the second grouping of outer subpixels through the second plurality of transfer gates. The image charge in the inner subpixel is received by the first, second, or both floating diffusions through respective transfer gates.

公开(公告)号：US20210305298A1

公开(公告)日：2021-09-30

申请号：US16830078

申请日：2020-03-25

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Sing-Chung Hu ,  Seong Yeol Mun ,  Bill Phan

IPC: H01L27/146

Abstract: Image sensors include a photodiode disposed in a semiconductor substrate and a transistor operatively coupled to the photodiode. At least three substrate trench structures are formed in the semiconductor substrate, defining two nonplanar structures, each having a plurality of sidewall portions. An isolation layer includes at least three isolation layer trench structures, each being disposed in a respective one of the three substrate trench structures. A gate includes three fingers, each being disposed in a respective one of the three isolation layer trench structures. An electron channel of the transistor extends along the plurality of sidewall portions of the two nonplanar structures in a channel width plane.

公开(公告)号：US20210202553A1

公开(公告)日：2021-07-01

申请号：US16730756

申请日：2019-12-30

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Seong Yeol Mun

IPC: H01L27/146

Abstract: A fully depleted silicon on insulator (FDSOI) is employed to reduce diffusion leakage (e.g., gate induced drain leakage, junction leakage, etc.) associated with the diffusion regions of a pixel cell. The buried oxide (BOX) layer, for example, fully isolates the transistor channel region, such as an (N) channel region of the pixel cell from the photodiode(s) of the pixel region, eliminating the junction leakage path, thus leading to a reduction in diffusion leakage and an increase device operation speed. An increase of full well capacity can also be realized by the absence of isolation structure, such as trench isolation or isolation implant structure.

公开(公告)号：US10811453B1

公开(公告)日：2020-10-20

申请号：US16671608

申请日：2019-11-01

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Seong Yeol Mun ,  Bill Phan ,  Alireza Bonakdar

IPC: H01L27/146

Abstract: An image sensor includes a plurality of photodiodes arranged in rows and columns of a pixel array that is disposed in a semiconductor substrate. Individual photodiodes of the pixel array are configured to receive incoming light through a backside of the semiconductor substrate. A front side of the semiconductor substrate is opposite from the backside. A plurality of deep trench isolation (DTI) structures are formed laterally with respect to the photodiodes on the backside of the semiconductor substrate. The plurality of DTI structures are arranged between adjacent photodiodes. A plurality of pillar structures extend from a metal grid proximate to the backside and is formed proximate to the backside and aligned with the DTI structures.

公开(公告)号：US20250081656A1

公开(公告)日：2025-03-06

申请号：US18461320

申请日：2023-09-05

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Bill Phan ,  Duli Mao ,  Seong Yeol Mun

IPC: H01L27/146

Abstract: An image sensor is described. The image sensor comprises a plurality of pixels arranged to form an active pixel array, a plurality of contact pads disposed within a peripheral region of the image sensor that surrounds the active pixel array, and an optical structure disposed within the peripheral region between the plurality of contact pads and the active pixel array. The optical structure is adapted to mitigate stray light from reaching the active pixel array.

公开(公告)号：US11984464B2

公开(公告)日：2024-05-14

申请号：US16946842

申请日：2020-07-08

Applicant: OmniVision Technologies, Inc.

Inventor： Seong Yeol Mun ,  Yuanliang Liu

IPC: H01L27/146 ,  H01L21/762

CPC classification number: H01L27/1463 ,  H01L21/76224 ,  H01L27/14605 ,  H01L27/14607 ,  H01L27/14616 ,  H01L27/1464 ,  H01L27/14643

Abstract: Examples of the disclosed subject matter propose disposing trench isolation structure around the perimeter of the pixel transistor region of the pixel cell. The trench isolation structure includes front side (e.g., shallow and deep) trench isolation structure and back side deep trench isolation structure that abut against or contacts the bottom of front side deep trench isolation structure for isolating the pixel transistor channel of the pixel cell's pixel transistor region. The formation and arrangement of the trench isolation structure in the pixel transistor region forms a floating doped well region, containing, for example, a floating diffusion (FD) and source/drains (e.g., (N) doped regions) of the pixel transistors. This floating P-well region aims to reduce junction leakage associated with the floating diffusion region of the pixel cell.

公开(公告)号：US11869906B2

公开(公告)日：2024-01-09

申请号：US16946743

申请日：2020-07-02

Applicant: OmniVision Technologies, Inc.

Inventor： Seong Yeol Mun ,  Heesoo Kang

IPC: H01L27/146

CPC classification number: H01L27/1461 ,  H01L27/14643 ,  H01L27/14689

Abstract: A pixel cell with an elevated floating diffusion region is formed to reduce diffusion leakage (e.g., gate induced drain leakage, junction leakage, etc.). The floating diffusion region can be elevated by separating a doped floating diffusion region from the semiconductor substrate by disposing an intervening layer (e.g., undoped, lightly doped, etc.) on the semiconductor substrate and beneath the doped floating diffusion region. For instance, the elevated floating diffusion region can be formed by stacked material layers composed of a lightly or undoped base or intervening layer and a heavy doped (e.g., As doped) “elevated” layer. In some examples, the stacked material layers can be formed by first and second epitaxial growth layers.