Image sensor with shared gray code generator and parallel column arithmetic logic units

    公开(公告)号:US11431936B2

    公开(公告)日:2022-08-30

    申请号:US16854765

    申请日:2020-04-21

    Abstract: A readout circuit for use in an image sensor includes a plurality of comparators. Each one of the plurality of comparators is coupled to receive a ramp signal and a respective analog image data signal from a respective one of a plurality of column bit lines to generate a respective comparator output. Each one of a plurality of arithmetic logic units (ALUs) is coupled to receive phase-aligned Gray code (GC) outputs generated by a GC generator. Each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output. Each one of the plurality of ALUs is coupled to latch the phase-aligned GC outputs in response to the respective comparator output to generate a respective digital image data signal.

    Current injection for fast ramp start-up during analog-to-digital operations

    公开(公告)号:US10187602B2

    公开(公告)日:2019-01-22

    申请号:US16034226

    申请日:2018-07-12

    Abstract: An example method for fast ramp start-up during analog to digital conversion (ADC) includes opening a feedback bypass switch coupled to an amplifier to initiate an ADC operation, providing an injection current pulse to an inverting input of the amplifier, where the non-inverting input is coupled to a feedback bypass switch, integrating a first reference current coupled to the inverting input of the amplifier, where the integrating of the first reference current occurs due to the opening of the feedback bypass switch, and providing a reference voltage in response to the injection current pulse, the integrating of the first reference current, and a reference voltage coupled to a non-inverting input of the amplifier, where a level of the reference voltage is increased at least at initiation of the ADC operation in response to the injection current pulse.

    METHOD AND APPARATUS FOR DATA TRANSMISSION IN AN IMAGE SENSOR

    公开(公告)号:US20180255255A1

    公开(公告)日:2018-09-06

    申请号:US15446711

    申请日:2017-03-01

    CPC classification number: H04N5/3577 H04N5/3765 H04N5/378 H04N5/907

    Abstract: Methods and apparatuses for data transmission in an image sensor are disclosed herein. An example data transmission circuit may include a plurality of transmission banks coupled in series with a first one of the plurality of transmission banks coupled to function logic, where each of the plurality of transmission banks are coupled to provide image data to a subsequent transmission bank in a direction toward the function logic in response to a clock signal, a plurality of delays coupled in series, wherein each of the plurality of delays is associated with and coupled to a respective transmission bank of the plurality of transmission banks, and wherein the clock signal is received by each of the plurality of transmission banks after being delayed by a respective number of delays of the plurality of delays in relation to the function logic.

    CURRENT INJECTION FOR FAST RAMP START-UP DURING ANALOG-TO-DIGITAL OPERATIONS

    公开(公告)号:US20180167573A1

    公开(公告)日:2018-06-14

    申请号:US15376352

    申请日:2016-12-12

    CPC classification number: H04N5/378 H03K4/90 H03M1/34 H03M1/56 H03M1/66

    Abstract: An example method for fast ramp start-up during analog to digital conversion (ADC) includes opening a feedback bypass switch coupled to an amplifier to initiate an ADC operation, providing an injection current pulse to an inverting input of the amplifier, where the non-inverting input is coupled to a feedback bypass switch, integrating a first reference current coupled to the inverting input of the amplifier, where the integrating of the first reference current occurs due to the opening of the feedback bypass switch, and providing a reference voltage in response to the injection current pulse, the integrating of the first reference current, and a reference voltage coupled to a non-inverting input of the amplifier, where a level of the reference voltage is increased at least at initiation of the ADC operation in response to the injection current pulse.

    SAMPLE AND HOLD SWITCH DRIVER CIRCUITRY WITH SLOPE CONTROL

    公开(公告)号:US20220078360A1

    公开(公告)日:2022-03-10

    申请号:US17530316

    申请日:2021-11-18

    Abstract: A switch driver circuit includes a plurality of pullup transistors. The plurality of pullup transistors includes a first pullup transistor coupled between a voltage supply and a first output node. A plurality of pulldown transistors includes a first pulldown transistor coupled between the first output node and a ground node. A slope control circuit is coupled to the ground node. A plurality of global connection switches includes a first global connection switch coupled between the first output node and the slope control circuit.

    Sample and hold switch driver circuitry with slope control

    公开(公告)号:US11212467B2

    公开(公告)日:2021-12-28

    申请号:US16516067

    申请日:2019-07-18

    Abstract: A switch driver circuit includes a first transistor coupled between a voltage supply and a first output node. A second transistor is coupled between the first output node and a first discharge node. A first slope control circuit is coupled to the first discharge node to discharge the first discharge node at a first slope. A third transistor is coupled between the voltage supply and a second output node. A fourth transistor is coupled between the second output node and a second discharge node. A second slope control circuit coupled to the second discharge node to discharge the second discharge node at a second slope. The first and second slopes are mismatched.

    Current injection for fast ramp start-up during analog-to-digital operations

    公开(公告)号:US10051225B2

    公开(公告)日:2018-08-14

    申请号:US15376352

    申请日:2016-12-12

    CPC classification number: H04N5/378 H03K4/90 H03M1/34 H03M1/56 H03M1/66

    Abstract: An example method for fast ramp start-up during analog to digital conversion (ADC) includes opening a feedback bypass switch coupled to an amplifier to initiate an ADC operation, providing an injection current pulse to an inverting input of the amplifier, where the non-inverting input is coupled to a feedback bypass switch, integrating a first reference current coupled to the inverting input of the amplifier, where the integrating of the first reference current occurs due to the opening of the feedback bypass switch, and providing a reference voltage in response to the injection current pulse, the integrating of the first reference current, and a reference voltage coupled to a non-inverting input of the amplifier, where a level of the reference voltage is increased at least at initiation of the ADC operation in response to the injection current pulse.

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