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    Codec to reduce simultaneously switching outputs
    11.
    发明授权
    Codec to reduce simultaneously switching outputs 有权
    编解码器同时减少切换输出

    公开(公告)号：US09406364B2

    公开(公告)日：2016-08-02

    申请号：US14310269

    申请日：2014-06-20

    Applicant: Oracle International Corporation

    Inventor： Robert P. Masleid ,  Don Draper ,  Venkat Krishnaswamy ,  Paul Loewenstein

    IPC: G11C29/00 ,  G11C8/10 ,  G11C8/06

    CPC classification number: G11C8/10 ,  G06F11/1048 ,  G11C7/1006 ,  G11C8/06

    Abstract: Embodiments of an apparatus and method for encoding data are disclosed that may allow for reduced simultaneous switching output noise. The apparatus may include a row decode circuit, a column decode circuit, and a memory array. The row decode circuit and column decode circuits may be configured to decode a first portion and a second portion, respectively, of a given data word of a first plurality of data words, where each data word may include N data bits, and where N is an integer greater than one. The memory array may be configured to store a second plurality of data words where each data word may include M data bits, and where M is an integer greater than N. The memory array may be further configured to retrieve a given data word of the second plurality of data words dependent upon the decoded first and second portions.

    Abstract translation: 公开了一种用于编码数据的装置和方法的实施例，其可以允许降低的同时开关输出噪声。 该装置可以包括行解码电路，列解码电路和存储器阵列。 行解码电路和列解码电路可以被配置为分别解码第一多个数据字的给定数据字的第一部分和第二部分，其中每个数据字可以包括N个数据位，并且其中N是 大于1的整数。 存储器阵列可以被配置为存储第二多个数据字，其中每个数据字可以包括M个数据位，并且其中M是大于N的整数。存储器阵列还可以被配置为检索第二个数据字的给定数据字 取决于解码的第一和第二部分的多个数据字。

    Static random access memory circuit with step regulator
    12.
    发明授权
    Static random access memory circuit with step regulator 有权
    静态随机存取存储器电路与步进调节器

    公开(公告)号：US09013943B2

    公开(公告)日：2015-04-21

    申请号：US13683317

    申请日：2012-11-21

    Applicant: Oracle International Corporation

    Inventor： Robert P. Masleid

    IPC: G11C5/14

    CPC classification number: G11C5/14

    Abstract: Implementations of the present disclosure involve a circuit and/or method for providing a static random access memory (SRAM) component of a very large scale integration (VLSI) design, such as a microprocessor design. In particular, the present disclosure provides for an SRAM circuit that includes a step voltage regulator coupled to the SRAM circuit and designed to maintain a fixed-value voltage drop across the regulator rather than a fixed voltage across the load of the SRAM circuit. The fixed-value drop across the regulator allows the SRAM circuit to be operated at a low retention voltage to reduce leakage of the SRAM circuit while maintaining the parasitic decoupling capacitance across the power supply from the SRAM circuit to reduce power signal fluctuations. In addition, the regulator circuit coupled to the SRAM circuit may include a switch circuit to control the various states of the SRAM circuit.

    Abstract translation: 本公开的实现涉及用于提供诸如微处理器设计的非常大规模集成（VLSI）设计的静态随机存取存储器（SRAM）组件的电路和/或方法。 特别地，本公开提供了一种SRAM电路，其包括耦合到SRAM电路并被设计为在整个调节器上保持固定值的电压降而不是跨越SRAM电路的负载的固定电压的阶跃电压调节器。 调节器上的固定值降低允许SRAM电路以低保持电压工作，以减少SRAM电路的泄漏，同时保持来自SRAM电路的电源之间的寄生去耦电容，以减少功率信号波动。 此外，耦合到SRAM电路的调节器电路可以包括用于控制SRAM电路的各种状态的开关电路。

    Low-noise arrangement for very-large-scale integration differential input/output structures
    15.
    发明授权
    Low-noise arrangement for very-large-scale integration differential input/output structures 有权
    用于非常大规模集成差分输入/输出结构的低噪声布置

    公开(公告)号：US09543243B2

    公开(公告)日：2017-01-10

    申请号：US14536188

    申请日：2014-11-07

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： Robert P. Masleid ,  Donald Arthur Draper ,  Eben Kunz ,  Laura Kocubinski

    IPC: H01L23/52 ,  H01L23/522 ,  H01L23/00

    CPC classification number: H01L23/5226 ,  H01L23/5286 ,  H01L24/17 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: Embodiments of the invention provide low-noise arrangements for very-large-scale integration (VLSI) differential input/output (I/O) structures (I/O pins, solder bumps, vias, etc.). Novel geometries are described for arranging differential pairs of I/O structures in perpendicular or near-perpendicular “quads.” The geometries effectively place one differential pair on or near the perpendicular bisector of its adjacent differential pair, such that field cancellation and differential reception can substantially eliminate noise without the need for added spacing or shields. By exploiting these effects, embodiments can suppress noise, independent of I/O structure spacing, and arbitrarily small spacings are permitted. Such arrangements can be extended into running chains, and even further into arrays of parallel chains. The parallel chains can be separated by supply structures (e.g., power supply bumps, or the like), and such supply structures can supply power to the I/O circuits of the IC, while also shielding adjacent chains from each other.

    Abstract translation: 本发明的实施例提供用于非常大规模集成（VLSI）差分输入/输出（I / O）结构（I / O引脚，焊料凸块，通孔等））的低噪声布置。 描述了用于在垂直或接近垂直的“四边形”中布置差分对I / O结构的新颖几何形状。几何形状有效地将一个差分对放置在其相邻差分对的垂直平分线上或附近，使得场消除和差分接收可以 基本上消除噪音，而不需要添加间隔或屏蔽。 通过利用这些效果，实施例可以抑制独立于I / O结构间隔的噪声，并且允许任意小的间隔。 这种布置可以扩展到运行链，甚至可以扩展到并行链的阵列。 平行链可以由供应结构（例如，电源凸起等）分开，并且这样的供应结构可以向IC的I / O电路供电，同时也将相邻的链彼此屏蔽。

    MULTIPLE ON-DIE COMMUNICATION NETWORKS
    16.
    发明申请
    MULTIPLE ON-DIE COMMUNICATION NETWORKS 审中-公开
    多功能通讯网络

    公开(公告)号：US20150281396A1

    公开(公告)日：2015-10-01

    申请号：US14336037

    申请日：2014-07-21

    Applicant: Oracle International Corporation

    Inventor： Paul Loewenstein ,  Robert P. Masleid ,  Stephen Phillips ,  Thirumalai Swamy Suresh

    IPC: H04L29/08

    CPC classification number: H04L67/32 ,  H04L67/2842

    Abstract: A method for communication among multiple on-die functional blocks using multiple communication networks is disclosed. The method may include sending a request from a first functional block via a first network. In response to receiving the request, a second functional block may respond to the first functional block via a second network. The second functional block may also send any requested data to the first functional block via a third network.

    Abstract translation: 公开了一种使用多个通信网络在多个片上功能块之间进行通信的方法。 该方法可以包括经由第一网络从第一功能块发送请求。 响应于接收到请求，第二功能块可以经由第二网络对第一功能块进行响应。 第二功能块还可以经由第三网络向第一功能块发送任何请求的数据。

    STATIC RANDOM ACCESS MEMORY CIRCUIT WITH STEP REGULATOR
    17.
    发明申请
    STATIC RANDOM ACCESS MEMORY CIRCUIT WITH STEP REGULATOR 有权
    带步进稳压器的静态随机存取电路

    公开(公告)号：US20140140147A1

    公开(公告)日：2014-05-22

    申请号：US13683317

    申请日：2012-11-21

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： Robert P. Masleid

    IPC: G11C7/12

    CPC classification number: G11C5/14

    Abstract: Implementations of the present disclosure involve a circuit and/or method for providing a static random access memory (SRAM) component of a very large scale integration (VLSI) design, such as a microprocessor design. In particular, the present disclosure provides for an SRAM circuit that includes a step voltage regulator coupled to the SRAM circuit and designed to maintain a fixed-value voltage drop across the regulator rather than a fixed voltage across the load of the SRAM circuit. The fixed-value drop across the regulator allows the SRAM circuit to be operated at a low retention voltage to reduce leakage of the SRAM circuit while maintaining the parasitic decoupling capacitance across the power supply from the SRAM circuit to reduce power signal fluctuations. In addition, the regulator circuit coupled to the SRAM circuit may include a switch circuit to control the various states of the SRAM circuit.

    Abstract translation: 本公开的实现涉及用于提供诸如微处理器设计的非常大规模集成（VLSI）设计的静态随机存取存储器（SRAM）组件的电路和/或方法。 特别地，本公开提供了一种SRAM电路，其包括耦合到SRAM电路并被设计为在整个调节器上保持固定值的电压降而不是跨越SRAM电路的负载的固定电压的阶跃电压调节器。 调节器上的固定值降低允许SRAM电路以低保持电压工作，以减少SRAM电路的泄漏，同时保持来自SRAM电路的电源之间的寄生去耦电容，以减少功率信号波动。 此外，耦合到SRAM电路的调节器电路可以包括用于控制SRAM电路的各种状态的开关电路。

    Variable run length encoding of a bit stream
    19.
    发明授权
    Variable run length encoding of a bit stream 有权
    位流的可变游程长度编码

    公开(公告)号：US09484949B1

    公开(公告)日：2016-11-01

    申请号：US14682227

    申请日：2015-04-09

    Applicant: Oracle International Corporation

    Inventor： Sadar Ahmed ,  Robert P. Masleid

    IPC: H03M5/14 ,  H04L25/49

    CPC classification number: H03M5/145 ,  H03M7/4037 ,  H04L25/4908

    Abstract: An apparatus and method for encoding data are disclosed that may allow for variable run length encoding of data to be transmitted. An ordered stream of data bits is received from a logic circuit, and N sequential data bits of the stream are selected, where N is a positive integer. Of the N sequential data bits, M sequential data bits are selected, wherein M is a positive integer less than N. The M sequential data bits are then encoded to generate a code word that includes P data bits, wherein P is a positive integer greater than M and less than N. The code word is then concatenated with a subset of the N sequential data bits that excludes the M sequential data bits to form a transmission word. A transmit unit then sends the data bits of the transmission word in a serial fashion.

    Abstract translation: 公开了一种用于编码数据的装置和方法，其可以允许要发送的数据的可变行程长度编码。 从逻辑电路接收有序的数据位流，并且选择流的N个顺序数据位，其中N是正整数。 在N个顺序数据位中，选择M个顺序数据位，其中M是小于N的正整数。然后对M个顺序数据位进行编码，以产生包含P个数据位的代码字，其中P是更大的正整数 并且小于N.然后将代码字与排除M个顺序数据位的N个顺序数据位的子集连接以形成传输字。 然后，发送单元以串行方式发送传输字的数据位。

    VARIABLE RUN LENGTH ENCODING OF A BIT STREAM
    20.
    发明申请
    VARIABLE RUN LENGTH ENCODING OF A BIT STREAM 有权
    一个位流的可变长度编码

    公开(公告)号：US20160301422A1

    公开(公告)日：2016-10-13

    申请号：US14682227

    申请日：2015-04-09

    Applicant: Oracle International Corporation

    Inventor： Sadar Ahmed ,  Robert P. Masleid

    IPC: H03M7/40

    CPC classification number: H03M5/145 ,  H03M7/4037 ,  H04L25/4908

    Abstract: An apparatus and method for encoding data are disclosed that may allow for variable run length encoding of data to be transmitted. An ordered stream of data bits is received from a logic circuit, and N sequential data bits of the stream are selected, where N is a positive integer. Of the N sequential data bits, M sequential data bits are selected, wherein M is a positive integer less than N. The M sequential data bits are then encoded to generate a code word that includes P data bits, wherein P is a positive integer greater than M and less than N. The code word is then concatenated with a subset of the N sequential data bits that excludes the M sequential data bits to form a transmission word. A transmit unit then sends the data bits of the transmission word in a serial fashion.

    Abstract translation: 公开了一种用于编码数据的装置和方法，其可以允许要发送的数据的可变行程长度编码。 从逻辑电路接收有序的数据位流，并且选择流的N个顺序数据位，其中N是正整数。 在N个顺序数据位中，选择M个顺序数据位，其中M是小于N的正整数。然后对M个顺序数据位进行编码，以产生包含P个数据位的代码字，其中P是更大的正整数 并且小于N.然后将代码字与排除M个顺序数据位的N个顺序数据位的子集连接以形成传输字。 然后，发送单元以串行方式发送传输字的数据位。

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