摘要:
A method for designing an interconnect, the method includes determining an amount of input ports, an amount of output ports; characterized by selecting multiple modular components such as to form an interconnect, whereas each modular component is selected from a group of modular components that are verified by parametric verification environment. An interconnect that includes multiple input ports and multiple output ports, characterized by including multiple modular components; whereas each modular component is adapted to support a certain point-to-point protocol; whereas at least one modular component includes a sampling circuit and a bypass circuit, whereas the sampling circuit is selectively bypassed by the bypass circuit.
摘要:
An object management system that includes at least one object identification device to be secured to an associated object. The object identification devices provide radio frequency signals containing object identification codes. The system includes at least one user identification device providing a radio frequency signal containing a user identification code and a control unit having a reader for receiving and reading the signals provided by the user identification devices and the object identification devices. One aspect provides a remote unit that communicates directly with the control unit to receive information associated with a condition of the object management system at a location remote from the control unit. The remote unit is further configured to be carried by a user and configured to communicate information and/or an alert to the user, wherein the information and/or the alert is associated with the condition of the object management system.
摘要:
A pipelined device and method for executing transactions in a pipelined device, the method includes: setting limiter thresholds that define a maximal amount of pending transaction requests to be provided from one pipeline stage to another pipeline stage; executing an application while monitoring the performance of a device that comprises pipeline limiters; wherein the executing includes: selectively transferring transaction requests from one stage of the pipeline to another in response to the limiter thresholds, arbitrating between transaction requests at a certain pipeline stage, and executing selected transaction requests provided by the arbitrating.
摘要:
Interfacing between radio units in a base station in a mobile communication system uses a common public radio interface CPRI for streaming IQ data samples arranged in lanes. A separate serial interface sRIO is now additionally used for transferring selected data samples arranged in packets, the selected samples corresponding to selected lanes streamed between other radio units via the common public radio interface. In the radio unit, the selected data samples are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected data samples arranged in packets received via the serial interface are arranged in lanes. A system timer coupled to the CPRI generates a timebase for controlling the sRIO interface in order to have it synchronized. Advantageously the data sample transfer capacity of the streaming CPRI interface is extended using the packet based serial interface.
摘要:
A controller device can control the time of a slave sub-system in a chain in a base station system. The controller device comprises a slave transceiver for receiving/transmitting from/to a master sub-system, and a synchronization device for synchronizing a clock of the slave transceiver to a clock of the master sub-system based on the received signal received from the master sub-system. The synchronization circuitry comprises a clock input port for receiving an external clock signal from an external clock generator. At a received signal input port the received signal can be received from the master transceiver. A tracking loop couples the received signal input and the second phase input to a control input of a controllable PLL, for providing a negative feedback which controls a phase and/or frequency of the feedback signal to counter the phase and or frequency error between the external clock signal and the received signal.
摘要:
An object management system that includes at least one object identification device to be secured to an associated object. The object identification devices provide radio frequency signals containing object identification codes. The system includes at least one user identification device providing a radio frequency signal containing a user identification code and a control unit having a reader for receiving and reading the signals provided by the user identification devices and the object identification devices. One aspect provides a remote unit that communicates directly with the control unit to receive information associated with a condition of the object management system at a location remote from the control unit. The remote unit is further configured to be carried by a user and configured to communicate information and/or an alert to the user, wherein the information and/or the alert is associated with the condition of the object management system.
摘要:
A device and a method, the device has transaction scheduling capabilities, and includes: (i) a memory unit adapted to output data at a first data rate, (ii) a data transaction initiator adapted to receive data at a second data rate that is lower than the first data rate; (iii) a deep pipelined crossbar characterized by a latency; and (iv) a data rate converter connected between the deep pipelined crossbar and the data transaction initiator; wherein the data rate converter is adapted to schedule a transaction of data unit from the memory unit in response to the latency of the deep pipelined crossbar, the first data rate, the second data rate, and size of an available storage space, within the data rate converter allocated for storing data from the memory unit.
摘要:
Interfacing between radio units in a base station in a mobile communication system uses a common public radio interface CPRI for streaming IQ data samples and control data arranged in lanes. A separate serial interface sRIO is now additionally used for transferring selected control data arranged in packets to a controller, the selected control data being streamed between other radio units via the common public radio interface. In the radio unit, the selected control data are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected control data arranged in packets received via the serial interface are arranged in lanes to be streamed. Advantageously the control data of the streaming CPRI interface is seamlessly transferred to the controller via the packet based serial interface.
摘要:
A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor.
摘要:
Interfacing between radio units in a base station in a mobile communication system may use synchronized clocks. A controller device has a tracking clock circuit for generating a transmit clock, the tracking clock circuit comprising a clock input for receiving a reference clock and a sync input for receiving an external synchronization signal. A multiplying phase locked loop generates the transmit clock in dependence on the reference clock and a divider output of a controllable divider coupled to the transmit clock. A tracking loop has a phase detector coupled to the sync input and the divider output for detecting a phase error between the external synchronization signal and transmit clock, and a phase control circuit for generating a phase control signal based on the phase error, the phase control signal being coupled to a control input of the controllable divider for adapting the division function.