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    Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate
    11.
    发明授权
    Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate 有权
    用于制造不对称双栅极晶体管的方法，通过该方法可以在同一衬底上制造不对称和对称双栅极晶体管

    公开(公告)号：US08105906B2

    公开(公告)日：2012-01-31

    申请号：US12521377

    申请日：2007-12-28

    申请人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    发明人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    IPC分类号： H01L21/336

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L29/78645

    摘要： A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate transistor, and at least a second semiconducting block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block.

    摘要翻译： 一种用于制造具有一个或多个非对称双栅极晶体管的微电子器件的方法，包括：a）在至少包括形成双栅晶体管的第一栅极的第一半导体块的衬底上形成一个或多个结构，以及 至少第二半导体块，其被配置为形成所述双栅极晶体管的第二栅极，所述第一块和所述第二块位于至少一个半导体区的相对侧上，并且通过第一栅极介电区与所述半导体区分离;以及 分别为第二栅极介电区，以及b）使用相对于第一块选择性的至少一种注入，在结构中的至少一个给定结构的第二块中至少掺杂一个或多个半导体区域。

    SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable
    12.
    发明授权
    SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable 有权
    SRAM存储单元具有以多个级别集成的晶体管，其阈值电压VT可动态调整

    公开(公告)号：US08013399B2

    公开(公告)日：2011-09-06

    申请号：US12466733

    申请日：2009-05-15

    申请人： Olivier Thomas ,  Perrine Batude ,  Arnaud Pouydebasque ,  Maud Vinet

    发明人： Olivier Thomas ,  Perrine Batude ,  Arnaud Pouydebasque ,  Maud Vinet

    IPC分类号： H01L27/088

    CPC分类号： H01L27/1104 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203

    摘要： A static random access memory cell which, on a substrate surmounted by a stack of layers, including: a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor are connected to a word line and are arranged between a first bit line and a first storage node and a second bit line and a second storage node, respectively; and a second plurality of transistors forming a flip-flop and situated at least one other level of the stack, beneath said given level, wherein the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by an insulating region provided to enable coupling of said gate electrode and said channel region.

    摘要翻译： 一种静态随机存取存储单元，其在由层叠层所覆盖的衬底上，包括：第一多个晶体管，位于堆叠的给定电平，其中至少一个第一存取晶体管和至少一个第二存取晶体管连接 分别布置在第一位线和第一存储节点以及第二位线和第二存储节点之间; 以及第二多个晶体管，其形成触发器并且位于所述给定电平以下的所述堆叠的至少另一个电平，其中所述第二多个晶体管的晶体管每个包括位于与所述晶体管的晶体管的沟道区相对的栅电极 所述第一多个晶体管并且由所述沟道区域与被设置成能够耦合所述栅极电极和所述沟道区域的绝缘区域分离。

    METHOD FOR MAKING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE
    13.
    发明申请
    METHOD FOR MAKING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE 有权
    用不对称和对称双栅极晶体管制作不对称双栅极晶体管的方法可以在相同的基板上

    公开(公告)号：US20100317167A1

    公开(公告)日：2010-12-16

    申请号：US12521311

    申请日：2007-12-28

    申请人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    发明人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    IPC分类号： H01L21/336

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L29/78645

    摘要： A method for fabricating a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of said double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block, the second block being covered by a hard mask, a critical dimension of the hard mask being larger than the critical dimension of the second block.

    摘要翻译： 一种用于制造具有一个或多个双栅极晶体管的微电子器件的方法，包括：a）在至少包括构成为形成双栅极晶体管的第一栅极的第一块的至少一个衬底上形成一个或多个结构，并且至少 第二块，其被配置为形成所述双栅极的第二栅极，所述第一块和所述第二块位于至少一个半导体区的相对侧上，并且通过第一栅极介电区和第二栅极电介质与所述半导体区分离 并且b）使用相对于第一块选择性的至少一种植入，在所述结构中掺杂至少一个给定结构的第二块中的至少一个或多个半导体区域，所述第二块被硬掩模覆盖， 硬掩模的临界尺寸大于第二块的临界尺寸。

    Method for making asymmetric double-gate transistors
    15.
    发明授权
    Method for making asymmetric double-gate transistors 有权
    制造非对称双栅晶体管的方法

    公开(公告)号：US08399316B2

    公开(公告)日：2013-03-19

    申请号：US12521233

    申请日：2007-12-28

    申请人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    发明人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    IPC分类号： H01L21/00

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L29/78645

    摘要： A method for making a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least one first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of the double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively; and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least a first implantation selective relative to the first block, the implantation being done on a first side of the given structure, the part of the structure on the other side of the normal to the principal plane of the substrate passing through the semiconducting zone not being implanted.

    摘要翻译： 一种用于制造具有一个或多个双栅极晶体管的微电子器件的方法，包括：a）在衬底上形成一个或多个结构，所述衬底包括至少一个构造成形成双栅极晶体管的第一栅极的第一块，并且至少 配置成形成双栅极的第二栅极的第二块，第一块和第二块位于至少一个半导体区的相对侧上，并且通过第一栅极介电区和第二栅极电介质与半导体区分离 区; 以及b）使用相对于所述第一块选择性的至少第一注入，在所述结构中掺杂至少一个给定结构的所述第二块中的至少一个或多个半导体区域，所述注入在给定结构的第一侧上进行 在通过半导电区域的衬底的主平面的法线的另一侧的结构的一部分未被植入。

    Memory cell provided with dual-gate transistors, with independent asymmetric gates
    16.
    发明授权
    Memory cell provided with dual-gate transistors, with independent asymmetric gates 有权
    具有双栅极晶体管的存储单元，具有独立的非对称栅极

    公开(公告)号：US08116118B2

    公开(公告)日：2012-02-14

    申请号：US12005666

    申请日：2007-12-26

    申请人： Olivier Thomas ,  Maud Vinet

    发明人： Olivier Thomas ,  Maud Vinet

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/785

    摘要： The invention concerns a random access memory cell comprising: at least one first plurality of symmetrical dual-gate transistors (TL1T, TL1F, TD1T, TD1F, TL2T, TL2F) forming a flip-flop, at least a first asymmetric dual-gate access transistor (TA1T, TAW1T) and at least a second asymmetric dual-gate access transistor (TA1F, TAW1F) disposed respectively between a first bit line (BLT, WBLT) and a first storage node (T), and between a second bit line (BLF, WBLF) and a second storage node (F), a first gate of the first access transistor (TA1T, TAW1T) and a first gate of the second access transistor (TA1F, TAW1F) being connected to a first word line (WL, WWL) able to route a biasing signal, a second gate (TA1F, TAW1F) of the first access transistor connected to the second storage node (F) and a second gate of the second access transistor connected to the first storage node (T).

    摘要翻译： 本发明涉及一种随机存取存储单元，包括：形成触发器的至少一个第一对称双栅极晶体管（TL1T，TL1F，TD1T，TD1F，TL2T，TL2F），至少第一不对称双栅极存取晶体管 （TA1T，TAW1T）和分别布置在第一位线（BLT，WBLT）和第一存储节点（T）之间以及第二位线（BLF）之间的至少第二非对称双栅极存取晶体管（TA1F，TAW1F） ，WBLF）和第二存储节点（F），第一存取晶体管的第一栅极（TA1T，TAW1T）和第二存取晶体管的第一栅极（TA1F，TAW1F）连接到第一字线（WL，WWL ）能够路由偏置信号，连接到第二存储节点（F）的第一存取晶体管的第二栅极（TA1F，TAW1F）和连接到第一存储节点（T）的第二存取晶体管的第二栅极。

    METHOD FOR FABRICATING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE
    17.
    发明申请
    METHOD FOR FABRICATING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE 有权
    用不对称和对称双栅极晶体管制造不对称双栅极晶体管的方法可以在同一基板上

    公开(公告)号：US20100320541A1

    公开(公告)日：2010-12-23

    申请号：US12521377

    申请日：2007-12-28

    申请人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    发明人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8244

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L29/78645

    摘要： A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate transistor, and at least a second semiconducting block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block.

    摘要翻译： 一种用于制造具有一个或多个非对称双栅极晶体管的微电子器件的方法，包括：a）在至少包括形成双栅晶体管的第一栅极的第一半导体块的衬底上形成一个或多个结构，以及 至少第二半导体块，其被配置为形成所述双栅极晶体管的第二栅极，所述第一块和所述第二块位于至少一个半导体区的相对侧上，并且通过第一栅极介电区与所述半导体区分离;以及 分别为第二栅极介电区，以及b）使用相对于第一块选择性的至少一种注入，在结构中的至少一个给定结构的第二块中至少掺杂一个或多个半导体区域。

    METHOD FOR MAKING ASYMMETRIC DOUBLE-GATE TRANSISTORS
    18.
    发明申请
    METHOD FOR MAKING ASYMMETRIC DOUBLE-GATE TRANSISTORS 有权
    制造非对称双栅极晶体管的方法

    公开(公告)号：US20100178743A1

    公开(公告)日：2010-07-15

    申请号：US12521233

    申请日：2007-12-28

    申请人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    发明人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    IPC分类号： H01L21/336

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L29/78645

    摘要： A method for making a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least one first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of the double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively; and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least a first implantation selective relative to the first block, the implantation being done on a first side of the given structure, the part of the structure on the other side of the normal to the principal plane of the substrate passing through the semiconducting zone not being implanted.

    摘要翻译： 一种用于制造具有一个或多个双栅极晶体管的微电子器件的方法，包括：a）在衬底上形成一个或多个结构，所述衬底包括至少一个构造成形成双栅极晶体管的第一栅极的第一块，并且至少 配置成形成双栅极的第二栅极的第二块，第一块和第二块位于至少一个半导体区的相对侧上，并且通过第一栅极介电区和第二栅极电介质与半导体区分离 区; 以及b）使用相对于所述第一块选择性的至少第一注入，在所述结构中掺杂至少一个给定结构的所述第二块中的至少一个或多个半导体区域，所述注入在给定结构的第一侧上进行 在通过半导电区域的衬底的主平面的法线的另一侧的结构的一部分未被植入。

    METHOD FOR FABRICATING MICROELECTRONIC DEVICES WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER ACTIVE REGIONS
    20.
    发明申请
    METHOD FOR FABRICATING MICROELECTRONIC DEVICES WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER ACTIVE REGIONS 有权
    用于在有源区域部分地形成隔离斜面的微电子器件制造方法

    公开(公告)号：US20150294903A1

    公开(公告)日：2015-10-15

    申请号：US14425891

    申请日：2012-09-05

    申请人： Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet ,  Romain Wacquez

    发明人： Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet ,  Romain Wacquez

    IPC分类号： H01L21/762 ,  H01L21/306 ,  H01L21/265 ,  H01L21/84

    CPC分类号： H01L21/76283 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/84

    摘要： A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.

    摘要翻译： 一种在包括第一半导体层，电介质层和第二半导体层的衬底中制造微电子器件的方法，包括以下步骤：通过所述第一半导体层，所述电介质层和所述第一半导体层的厚度的一部分蚀刻沟槽 从而在所述第一半导体层中限定所述微电子器件的一个有源区域，在所述沟槽的一个或多个侧壁中的离子注入，在所述第二半导体层的水平处，修改所述晶体学性质和/或所述第二半导体层， 注入半导体的化学性质，蚀刻注入的半导体，使得沟槽的至少一部分在有源区的一部分下方延伸，用电介质材料填充沟槽，形成围绕有源区的隔离沟槽，并且包括 在有源区域的一部分下延伸的部分。