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公开(公告)号：US4097824A
公开(公告)日：1978-06-27
申请号：US772677
申请日：1977-02-28
摘要： A variable equalizer adapted to be fabricated in an integrated circuit structure and having improved compensation characteristics comprises a parallel connection of two circuits, one including a series connection of a first impedance circuit (impedance: Zy) and an input A.C. signal source circuit having a voltage v.sub.i, the other comprising a series connection of a second impedance circuit (impedance: Z.sub.x) and an A.C. signal source circuit having a voltage amplitude v.sub.z which is equal to v.sub.i (K/Z.sub.y).sup.2, where K is a constant, and the second impedance circuit, consists of a variable resistor.
摘要翻译： 适于以集成电路结构制造并具有改进的补偿特性的可变均衡器包括两个电路的并联连接，一个包括第一阻抗电路（阻抗：Zy）的串联连接和具有电压的输入AC信号源电路 vi，另一个包括第二阻抗电路（阻抗：Zx）和具有等于vi（K / Zy）2的电压幅度vz的AC信号源电路的串联连接，其中K是常数，第二 阻抗电路由可变电阻组成。
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公开(公告)号：US5815502A
公开(公告)日：1998-09-29
申请号：US581966
申请日：1996-01-02
IPC分类号： G06F13/00 , H04L12/801 , H04L12/811 , H04L12/911 , H04L29/06 , H04L29/08 , H04M11/08 , H04N7/50 , H04N7/56 , H04N21/21 , H04N21/23 , H04N21/6377 , H04N21/658 , H04Q11/04 , H04J3/22
CPC分类号： H04L47/25 , H04L12/54 , H04L47/10 , H04L49/90 , H04L49/9047 , H04M11/08 , H04N19/115 , H04N19/152 , H04N19/164 , H04N19/184 , H04N19/61 , H04N21/21 , H04N21/23 , H04N21/6377 , H04N21/658 , H04N7/56 , H04Q11/04 , H04N19/146 , H04N19/50
摘要： A method and system for information processing in a bidirectional information transmission system, particularly for transmitting information in accordance with a change in a transmission capacity of a transmission line. A system is provided which can change an information transmission rate in accordance with a room capacity of a transmission line. This information transmission system includes a plurality of information providers, a plurality of information receivers, an information storage and distribution unit connected to the information providers and receivers, and a plurality of information transmission lines for information transmission between the information providers and receivers and the information storage and distribution unit, wherein the information transmission rate of each information transmission line is changed.
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公开(公告)号：US5515368A
公开(公告)日：1996-05-07
申请号：US226301
申请日：1994-04-12
IPC分类号： G06F13/00 , H04L12/801 , H04L12/811 , H04L12/911 , H04L29/06 , H04L29/08 , H04M11/08 , H04N7/50 , H04N7/56 , H04N21/21 , H04N21/23 , H04N21/6377 , H04N21/658 , H04Q11/04 , H04J3/22
CPC分类号： H04L47/25 , H04L12/54 , H04L47/10 , H04L49/90 , H04L49/9047 , H04M11/08 , H04N19/115 , H04N19/152 , H04N19/164 , H04N19/184 , H04N19/61 , H04N21/21 , H04N21/23 , H04N21/6377 , H04N21/658 , H04N7/56 , H04Q11/04 , H04N19/146 , H04N19/50
摘要： A method and system for information processing in a bidirectional information transmission system, particularly for transmitting information in accordance with a change in a transmission capacity of a transmission line. A system is provided which can change an information transmission rate in accordance with a room capacity of a transmission line. This information transmission system includes a plurality of information providers, a plurality of information receivers, an information storage and distribution unit connected to the information providers and receivers, and a plurality of information transmission lines for information transmission between the information providers and receivers and the information storage and distribution unit, wherein the information transmission rate of each information transmission line is changed.
摘要翻译： 一种双向信息传输系统中信息处理的方法和系统，特别是用于根据传输线的传输容量的变化发送信息。 提供一种可以根据传输线的房间容量改变信息传输速率的系统。 该信息传输系统包括多个信息提供者，多个信息接收者，连接到信息提供者和接收者的信息存储和分配单元，以及用于在信息提供者和接收者之间进行信息传输的多条信息传输线以及信息 存储和分配单元，其中每个信息传输线的信息传输速率改变。
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14.发明授权
公开(公告)号：US5430733A
公开(公告)日：1995-07-04
申请号：US452511
申请日：1989-12-19
申请人： Yoshitaka Takasaki
发明人： Yoshitaka Takasaki
CPC分类号： H04L25/4908
摘要： Data transmission and recovery, in either the optical or the electrical domain, can be accomplished with mBnB encoding with the violation of one or more of the n code pulses for multiplexing overhead signals, with a carried clock being indicated by periodic fixed position transitions, and with both extraction of the clock and demultiplexing of the overhead signals being accomplished with only logical processing and signal delay. For the above, transmission and processing in only the optical domain can be easily obtained as well as a circuitry that can be constructed cheaply and on a small scale, particularly by integration on a single substrate. The logical processing involves logical combinations of two or more of the received encoded signal, a delay of the received encoded signal, an output of a previous logical combination, and a delayed output of a previous combination, an extracted clock, and a frequency division or a frequency multiplication of an extracted clock.
摘要翻译： 在光或电域中的数据传输和恢复可以用mBnB编码来实现，其中违反一个或多个用于复用开销信号的n个码脉冲，携带时钟由周期性固定位置转换指示，以及 同时提取时钟并且只用逻辑处理和信号延迟来完成开销信号的解复用。 对于上述，可以容易地获得仅在光学域中的传输和处理，以及可以廉价且小规模地构建的电路，特别是通过集成在单个基板上。 逻辑处理涉及接收到的编码信号中的两个或更多个，接收到的编码信号的延迟，先前逻辑组合的输出和先前组合的延迟输出，提取的时钟和分频或 提取时钟的倍频。
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公开(公告)号：US4410980A
公开(公告)日：1983-10-18
申请号：US289106
申请日：1981-07-31
申请人： Yoshitaka Takasaki , Mitsuo Tanaka
发明人： Yoshitaka Takasaki , Mitsuo Tanaka
CPC分类号： H04J3/16 , H04J3/073 , H04L25/4912 , H04L5/24
摘要： In a time division multiplexing system for multiplexing a plurality of channels having mutually-independent bit rates, the improvement wherein the pulse signals of each channel are converted into codes so that the information "1" is represented by a pulse having a width of two consecutive transmission clock periods ("0,0" or "1,1") the information "0" is represented by a pluse having a width of a single transmission clock period ("0" or "1"), and polarities of adjacent pulses are always different from each other; the pulse signals are compressed time-wise in a frame unit; and a frame synchronizing signal and a channel synchronizing signal, each consisting of marks or spaces having a duration of at least three consecutive transmission clock periods, are added to the intervals between the time-compressed frames to thereby perform time division multiplexing.
摘要翻译： 在用于对具有相互独立的比特率的多个信道进行多路复用的时分复用系统中，每个信道的脉冲信号被转换成代码的改进，使得信息“1”由具有两个连续宽度的脉冲表示 传输时钟周期（“0,0”或“1,1”）信息“0”由具有单个传输时钟周期（“0”或“1”）的宽度的宽带和相邻脉冲的极性 总是相互不同; 脉冲信号以帧为单位被时间压缩; 并且每个由具有至少三个连续传输时钟周期的持续时间的标记或空间组成的帧同步信号和信道同步信号相加在时间压缩帧之间的间隔中，从而进行时分复用。
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公开(公告)号：US4204176A
公开(公告)日：1980-05-20
申请号：US893014
申请日：1978-04-03
CPC分类号： H04B3/145
摘要： A variable equalizer whose frequency characteristic varies in a range of 1-1/Y(f).sup.2when the gain x of a variable amplifier varies from 0 (zero) to .infin. (infinity), and which reduces the number of shaping networks for the variable frequency characteristic.It is constructed of a forward pass circuit which consists of a variable amplifier and a frequency-dependent first circuit connected in the order mentioned between input and output terminals, a feedback pass circuit which is dependent upon the frequency and which feeds-back an output of the variable amplifier to an input thereof, and a feed forward pass circuit which is independent of the frequency and which feeds forward part of the input of the variable amplifier to an output of the first circuit.
摘要翻译： 当可变放大器的增益x从0（零）到INFINITY（无穷大）变化时，其频率特性在1-1 / Y（f）2的范围内变化的可变均衡器，并且这减少了 可变频率特性。 它由正向电路构成，该正向电路由可变放大器和按照输入和输出端之间的顺序连接的频率依赖的第一电路组成，反馈通道电路取决于频率，并且反馈输出 可变放大器到其输入端，以及前馈传输电路，其独立于频率，并且将可变放大器的输入的前部部分馈送到第一电路的输出。
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17.发明授权
公开(公告)号：US5042027A
公开(公告)日：1991-08-20
申请号：US404535
申请日：1989-09-08
申请人： Akihiko Takase , Masahiro Takatori , Yoshiaki Takemura , Naoya Kobayashi , Yasushi Sawada , Yukio Nakano , Yasushi Takahashi , Masahiro Koya , Yoshitaka Takasaki
发明人： Akihiko Takase , Masahiro Takatori , Yoshiaki Takemura , Naoya Kobayashi , Yasushi Sawada , Yukio Nakano , Yasushi Takahashi , Masahiro Koya , Yoshitaka Takasaki
IPC分类号： H04M3/36 , H04L12/24 , H04L12/801 , H04L12/911 , H04M3/00 , H04Q3/66
CPC分类号： H04L45/00 , H04Q3/66 , H04Q2213/13141 , H04Q2213/13164 , H04Q2213/13166 , H04Q2213/13332 , H04Q2213/13353
摘要： A communication network system includes a communication line, a plurality of communication stations each having a node coupled to the communication line and a network controller coupled to the stations for controlling routing for communication messages between nodes. In one embodiment, the messages are sent from plural terminals connected with each node along with communication performance prerequisites. The communication performance prerequisites for a communication message are discriminated in the node which receives the message. Traffic in various routes between the nodes is continually measured in the communication stations and the measuring results are stored in a database storage unit. Future traffic in the various routes is predicted on the basis of the information on the continually measured traffic by the use of a predetermined algorithm and stored in the storage unit for use in determination of routes for communication messages on the basis of the result of the communication performance prerequisites discrimination and predetermined criteria with respect to the updated information on the predicted traffic in the storage unit.
摘要翻译： 通信网络系统包括通信线路，多个通信站，每个通信站具有耦合到通信线路的节点，以及耦合到该站点的网络控制器，用于控制节点之间的通信消息的路由。 在一个实施例中，从与每个节点连接的多个终端以及通信性能先决条件发送消息。 通信消息的通信性能先决条件在接收消息的节点中被区分。 在通信站中连续测量节点之间的各种路由的流量，并将测量结果存储在数据库存储单元中。 基于通过使用预定算法的连续测量的业务的信息来预测各种路线中的未来业务，并且存储在存储单元中以用于基于通信的结果确定通信消息的路由 性能先决条件判定和关于存储单元中预测业务量的更新信息的预定标准。
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公开(公告)号：US5023604A
公开(公告)日：1991-06-11
申请号：US233096
申请日：1988-08-17
申请人： Akihiko Takase , Yoshitaka Takasaki
发明人： Akihiko Takase , Yoshitaka Takasaki
摘要： The invention provides a communication method and system for use in a network for digital data exchange/transfer through a circuit switched network. According to the method and system, a call is given the attribute of an intermittent transfer mode, and a device for identifying attributes is provided on network controls in connection paths so that the network control establishes a path only in response to a data transfer request from identified call and releases the path when the call is held on standby for data transfer.
摘要翻译： 本发明提供一种在网络中用于通过电路交换网络进行数字数据交换/传输的通信方法和系统。 根据该方法和系统，给予间歇传送模式的属性的呼叫，并且在连接路径中的网络控制上提供用于识别属性的设备，使得网络控制仅响应于来自 当呼叫持续待机以进行数据传输时，识别呼叫并释放路径。
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公开(公告)号：US4796281A
公开(公告)日：1989-01-03
申请号：US919458
申请日：1986-10-16
申请人： Yoshitaka Takasaki
发明人： Yoshitaka Takasaki
CPC分类号： H04L25/05 , H04J3/073 , H04N21/234309 , H04N21/440218
摘要： A digital signal transmission system which converts first digital signals having a given bit rate into second digital signals having a predetermined bit rate to transmit them. The first digital signals are written into a buffer memory at a bit rate of the first digital signals, and the written signals are read from the first buffer memory at a bit rate of said second digital signals. The reading of the digital signals is carried out with a clock signal which consists of synchronous portions that read the written signals at any time and asynchronous portions that read the written signals depending upon the condition of the written signals. The second digital signals are sent after adding a data signal to the asynchronous portions of the digital signals. A second buffer memory receives the sent second digital signals and temporarily stores them by writing the second digital signals at the bit rate of said second digital signals, and reading the written signals from the second buffer memory at a bit rate of the third digital signals, the reading of the third digital signals depending upon signals of the asynchronous portions of the second digital signals.
摘要翻译： 一种数字信号传输系统，其将具有给定比特率的第一数字信号转换成具有预定比特率的第二数字信号以发送它们。 第一数字信号以第一数字信号的比特率写入缓冲存储器，并且以所述第二数字信号的比特率从第一缓冲存储器读取写入的信号。 数字信号的读取由时钟信号执行，该时钟信号由随时读取写入信号的同步部分和根据写入信号的条件读取写入信号的异步部分组成。 在将数据信号添加到数字信号的异步部分之后发送第二数字信号。 第二缓冲存储器接收所发送的第二数字信号，并通过以所述第二数字信号的比特率写入第二数字信号来临时存储它们，并以第三数字信号的比特率从第二缓冲存储器读取写入的信号， 根据第二数字信号的异步部分的信号读取第三数字信号。
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公开(公告)号：US4459698A
公开(公告)日：1984-07-10
申请号：US358437
申请日：1982-03-15
CPC分类号： H04L25/03019
摘要： A small-sized LSI variable equalizer is provided for accurately equalizing waveforms of signals transmitted via transmission lines of different distances. Variable equalizer units capable of stepwise changing the equalizing characteristics thereof are connected in series with each other with the variable equalizer units having variable step widths different from each other. An output signal of the variable equalizer units is compared with a reference signal to convert the comparison output signal to a digital signal which includes an upper order bits and lower order bits, whereby one of the equalizer units which has a wide variable step width is controlled by the upper order bits and the other of the equalizer units which has a narrow variable step width is controlled by the lower order bits.
摘要翻译： 提供小型LSI可变均衡器，用于精确地均衡通过不同距离的传输线传输的信号的波形。 能够逐步改变其均衡特性的可变均衡器单元彼此串联连接，而可变均衡器单元具有彼此不同的可变步长。 将可变均衡器单元的输出信号与参考信号进行比较，以将比较输出信号转换为包括高阶位和低位位的数字信号，由此控制具有宽可变步长的均衡器单元之一 通过较低阶比特和具有窄可变步宽的均衡器单元中的另一个由较低阶比特来控制。
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