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公开(公告)号：US4410980A
公开(公告)日：1983-10-18
申请号：US289106
申请日：1981-07-31
申请人： Yoshitaka Takasaki , Mitsuo Tanaka
发明人： Yoshitaka Takasaki , Mitsuo Tanaka
CPC分类号： H04J3/16 , H04J3/073 , H04L25/4912 , H04L5/24
摘要： In a time division multiplexing system for multiplexing a plurality of channels having mutually-independent bit rates, the improvement wherein the pulse signals of each channel are converted into codes so that the information "1" is represented by a pulse having a width of two consecutive transmission clock periods ("0,0" or "1,1") the information "0" is represented by a pluse having a width of a single transmission clock period ("0" or "1"), and polarities of adjacent pulses are always different from each other; the pulse signals are compressed time-wise in a frame unit; and a frame synchronizing signal and a channel synchronizing signal, each consisting of marks or spaces having a duration of at least three consecutive transmission clock periods, are added to the intervals between the time-compressed frames to thereby perform time division multiplexing.
摘要翻译： 在用于对具有相互独立的比特率的多个信道进行多路复用的时分复用系统中，每个信道的脉冲信号被转换成代码的改进，使得信息“1”由具有两个连续宽度的脉冲表示 传输时钟周期（“0,0”或“1,1”）信息“0”由具有单个传输时钟周期（“0”或“1”）的宽度的宽带和相邻脉冲的极性 总是相互不同; 脉冲信号以帧为单位被时间压缩; 并且每个由具有至少三个连续传输时钟周期的持续时间的标记或空间组成的帧同步信号和信道同步信号相加在时间压缩帧之间的间隔中，从而进行时分复用。
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公开(公告)号：US4504943A
公开(公告)日：1985-03-12
申请号：US408806
申请日：1982-08-17
CPC分类号： H04J3/1629 , H04L5/22
摘要： In order to enhance the general purposeness of a time domain multiplexer for digital channel signals of unequal bit rates, the time domain multiplexer is constructed of a plurality of channel units which provide information signals and bit rate signals of input channel signals, a plurality of logic circuits which multiplex the information signals from the channel units, and a control circuit which selects and combines the logic circuits in accordance with the bit rate signal so as to construct a multiplexer conforming with the bit rate.
摘要翻译： 为了增强时域多路复用器对不同比特率的数字信道信号的一般目的性，时域多路复用器由多个信道单元构成，这些信道单元提供输入信道信号的信息信号和比特率信号，多个逻辑 多路复用来自信道单元的信息信号的电路，以及根据比特率信号选择并组合逻辑电路以构成符合比特率的多路复用器的控制电路。
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公开(公告)号：US4970719A
公开(公告)日：1990-11-13
申请号：US233095
申请日：1988-08-17
申请人： Akihiko Takase , Yoshitaka Takasaki
发明人： Akihiko Takase , Yoshitaka Takasaki
IPC分类号： H04J3/16
CPC分类号： H04J3/1641 , Y10S370/916
摘要： A digital signal multiplexing apparatus comprising variable multiplexers each of which can alter a multiplexed channel format every call in compliance with a subscriber's request, a fixed multiplexer which has a multiplexing capacity integral times as large as the total multiplexing capacity of the variable multiplexers and the multiplexed channel format of which is fixed, and fixed multiplexed signal demultiplexers each of which fixedly demultiplexes signals in a capacity integral times as large as that of each of the variable multiplexers into signals in a capacity equal to the total capacity of the variable multiplexers, wherein the outputs of the fixed multiplexed signal demultiplexers are distributed to the variable multiplexers through a distributing switch network, and the outputs of the variable multiplexers are multiplexed by the fixed multiplexer.
摘要翻译： 一种数字信号复用装置，包括可变多路复用器，每个可以根据用户的请求改变每个呼叫的多路复用信道格式，固定多路复用器具有与可变多路复用器的总复用容量一样大的复用容量， 信道格式固定的固定多路复用信号解复用器，其中固定多路复用信号解复用器固定地将电容量与每个可变多路复用器的整数倍的电容多路分解成等于可变多路复用器的总容量的信号，其中， 固定复用信号解复用器的输出通过分配交换网络分配给可变多路复用器，并且可变多路复用器的输出由固定多路复用器复用。
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公开(公告)号：US4723312A
公开(公告)日：1988-02-02
申请号：US769971
申请日：1985-08-27
CPC分类号： H04B10/502
摘要： A high-speed light emitting diode driver circuit for optical communication systems, in which an impedance circuit is provided between the collector and emitter of a drive transistor, and another impedance circuit is provided on the emitter side. The light emitting diode is connected to the collector side of the drive transistor. The light emitting diode is driven by an input pulse signal applied to the base of the drive transistor.
摘要翻译： 用于光通信系统的高速发光二极管驱动电路，其中阻抗电路设置在驱动晶体管的集电极和发射极之间，另一个阻抗电路设置在发射极侧。 发光二极管连接到驱动晶体管的集电极侧。 发光二极管由施加到驱动晶体管的基极的输入脉冲信号驱动。
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公开(公告)号：US4604745A
公开(公告)日：1986-08-05
申请号：US578791
申请日：1984-02-10
摘要： A method of searching fault locations which is employed in a transmission system comprising a transmitting terminal having a transmitter for transmitting a digital signal; a receiving terminal having a receiver for receiving the digital signal; a plurality of repeaters which are placed between the transmitting and receiving terminals, and each of which receives and amplifies the digital signal from a preceding repeater section and deliver it to a subsequent repeater section; and a plurality of transmission lines for connecting the transmitter with the first repeater, the repeaters with each other and the final repeater with each other and the final repeater with the receiver, respectively. This method comprises the steps of coding an original signal to be transmitted in terms of two kinds of error detecting codes at the transmitting terminal to send out them from the transmitter; detecting an error of a received signal using one of the two kinds of error detecting codes at each repeater thereby to measure the error rate at one repeater section corresponding to each repeater; recoding a decoded received signal using the error detecting code employed to detect the error, and delivering it to a subsequent repeater section, and transmitting signals each of which represents the error rate at each repeater section measured at each repeater, to the transmitting terminal or receiving terminal.
摘要翻译： 一种搜索故障位置的方法，该传输系统包括具有用于发送数字信号的发射机的发射终端; 接收终端，具有接收数字信号的接收机; 放置在发送和接收终端之间的多个中继器，每个中继器从前一个中继器部分接收和放大数字信号，并将其传送到后续中继器部分; 以及多个传输线，用于将发射机与第一中继器连接，中继器彼此相连，最后中继器彼此相连，最后中继器分别与接收机相连。 该方法包括以下步骤：在发送终端根据两种错误检测码对要发送的原始信号进行编码，以从发送器发送出来; 使用每个中继器的两种错误检测码之一检测接收信号的误差，从而测量与每个中继器对应的一个中继器部分的错误率; 使用用于检测误差的检错码重新编码解码的接收信号，并将其传送到后续中继器部分，并且将发送信号分别表示在每个中继器测量的每个转发器部分处的错误率，发送到发送终端或接收 终奌站。
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公开(公告)号：US4320527A
公开(公告)日：1982-03-16
申请号：US66643
申请日：1979-08-15
申请人： Yoshitaka Takasaki
发明人： Yoshitaka Takasaki
摘要： A bit synchronizing system for generating a timing signal corresponding to a transmitted pulse signal is disclosed in which the transmitted pulse signal is converted into a signal in which the number of pulses successively assuming the same polarity is limited to permit detection of frequency, the converted signal is integrated, a peak of integrated values is detected, the output of a voltage-controlled clock generator for generating the timing signal is processed in a similar manner to detect a peak with respect to the output, and the clock generator is controlled by a voltage corresponding to a difference between these two peaks, whereby the frequency of clock signal coincides with the bit rate of the transmitted pulse signal.
摘要翻译： 公开了一种用于产生与发送的脉冲信号相对应的定时信号的位同步系统，其中发送的脉冲信号被转换成其中连续假设相同极性的脉冲数被限制以允许检测频率的信号，转换的信号 被集成，检测到积分值的峰值，以类似的方式处理用于产生定时信号的电压控制时钟发生器的输出，以检测相对于输出的峰值，并且时钟发生器由电压 对应于这两个峰值之间的差值，由此时钟信号的频率与发送的脉冲信号的比特率一致。
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7.发明授权
公开(公告)号：US5121381A
公开(公告)日：1992-06-09
申请号：US397553
申请日：1989-08-23
CPC分类号： H04J14/02 , H04Q11/0001 , H04J14/029 , H04Q2011/0081
摘要： Disclosed is an optical switching apparatus comprising means for converting serial optical or electrical signals into parallel signals in a time division mode, first and second time division switch groups and a space division switch group for cross connecting the signal of the optical or electrical signals, and means for generating the edited optical or electrical signals as serial signals again.
摘要翻译： 公开了一种光开关装置，包括用于将串行光信号或电信号以时分模式转换为并行信号的装置，第一和第二时分开关组以及用于交叉连接光信号或电信号的信号的空分开关组，以及 用于将编辑的光学或电信号再次生成为串行信号的装置。
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公开(公告)号：US5121244A
公开(公告)日：1992-06-09
申请号：US323711
申请日：1989-03-15
申请人： Yoshitaka Takasaki
发明人： Yoshitaka Takasaki
IPC分类号： H04B10/00 , H04B10/032 , H04B10/27
CPC分类号： H04J14/0291 , H04B10/032 , H04J14/0279
摘要： An optical subscriber network transmission system comprises a first optical transmission line transmitting information from center to a subscriber and a second optical transmission line transmitting information from to the subscriber to the center. A plurality of auxiliary optical transmission lines are disposed between the center and the subscriber.
摘要翻译： 光用户网络传输系统包括从中心向用户发送信息的第一光传输线和从用户向中心发送信息的第二光传输线。 多个辅助光传输线设置在中心和用户之间。
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公开(公告)号：US4262263A
公开(公告)日：1981-04-14
申请号：US036973
申请日：1979-05-08
申请人： Yoshitaka Takasaki
发明人： Yoshitaka Takasaki
摘要： A variable equalizer for compensating for the frequency characteristics of transmission media, comprising a plurality of variable circuits which are connected in cascade to an input terminal and which have the same variation characteristics, coefficient circuits which receive input and output signals of the variable circuits as inputs thereof and which multiply the inputs by coefficients, a plurality of impedance circuits which receive as inputs thereof signals with outputs of the coefficient circuits selectively combined and which have frequency-dependencies, and an adder circuit which adds outputs of the impedance circuits to provide an equalized signal as its output. No feedback circuit is required in the construction, and the plurality of variable circuits are constructed of the same circuits. Therefore, a variable equalizer which is capable of high-speed operation, whose circuit arrangement is simple and whose compensation accuracy is high is realized.
摘要翻译： 一种用于补偿传输介质的频率特性的可变均衡器，包括串联连接到输入端并具有相同变化特性的多个可变电路，接收可变电路的输入和输出信号作为输入的系数电路 并且将输入乘以系数，多个阻抗电路，其接收有选择地组合并且具有频率依赖性的系数电路的输出作为其输入的信号;以及加法器电路，其将所述阻抗电路的输出相加以提供均衡的 信号作为其输出。 该结构中不需要反馈电路，并且多个可变电路由相同的电路构成。 因此，实现了能够高速运行的可变均衡器，其电路布置简单并且其补偿精度高。
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公开(公告)号：US4122417A
公开(公告)日：1978-10-24
申请号：US796539
申请日：1977-05-13
CPC分类号： H04B3/145
摘要： To form a simple and economical variable equalizer, the equalizer is constructed of a differential amplifier having two input terminals to which an input signal to be equalized and an equalized output signal derived from the output terminal are applied, a first impedance circuit connected between the differential amplifier and the output terminal, and a series circuit having a second impedance circuit and a variable resistor connected in series between the output terminal and a ground terminal.
摘要翻译： 为了形成简单而经济的可变均衡器，均衡器由具有两个输入端的差分放大器构成，输入端被均衡，输入信号得到均衡的输出信号，第一阻抗电路连接在差分 放大器和输出端子，以及具有在输出端子和接地端子之间串联连接的第二阻抗电路和可变电阻器的串联电路。
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