公开(公告)号：US4759013A

公开(公告)日：1988-07-19

申请号：US905427

申请日：1986-09-10

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H04J1/05 ,  H04J4/00

CPC classification number: H04J4/005

Abstract: An FDM-TDM transmultiplexing system for a modulation/demodulation device which is applicable to a regenerative repeating system of a satellite or a ground radio communication system is disclosed which uses chirp-z-transform. A chirp filter is implemented with a digital circuit. The circuit scale of the digital chirp filter increases in proportion to a square root of the total number of channels N, enhancing miniaturization of an FDM-TDM transmultiplexer.

Abstract translation: 公开了一种适用于卫星或地面无线电通信系统的再生重复系统的用于调制/解调装置的FDM-TDM多路复用系统，其使用啁啾变换。 啁啾滤波器用数字电路实现。 数字线性调频滤波器的电路规模与总信道数N的平方根成比例地增加，从而增强了FDM-TDM多路复用器的小型化。

公开(公告)号：US4339725A

公开(公告)日：1982-07-13

申请号：US133744

申请日：1980-03-25

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H04L27/227 ,  H03D3/18 ,  H04L27/22

CPC classification number: H04L27/2272

Abstract: An N-phase PSK demodulator is disclosed wherein all circuits therein operate in a frequency band equal to or below the carrier band. The locally reproduced carrier is generated by a phase locked loop in combination with a frequency converter means and a divide-by-two frequency divider. The frequency converter means consists of n identical frequency converter circuits connected in series, where 2.sup.n =N. For a 2-phase PSK demodulator where n=1, the 2-phase PSK modulated wave is applied as a first input and the reproduced carrier divided by two is applied as a second input to the frequency converter circuit. A mixer and filter provide as an output the difference frequency between the first and second inputs. The latter output is multiplied by two and applied as the input to the phase locked loop. Where n>1, the first input of each frequency converter circuit except the first is the output from the preceeding circuit, and the output from the last frequency converter circuit is the input to the phase locked loop.

Abstract translation: 公开了一种N相PSK解调器，其中其中所有电路在等于或低于载波频带的频带内工作。 本地再现的载波由与频率转换器装置和分频二分频器组合的锁相环产生。 变频器装置由串联连接的n个相同的变频器电路组成，其中2n = N。 对于n = 1的2相PSK解调器，将2相PSK调制波作为第一输入，并将再生载波除以2作为第二输入施加到变频器电路。 混频器和滤波器作为输出提供第一和第二输入之间的差频。 后一个输出乘以2并作为输入施加到锁相环。 其中n> 1，除了第一个之外的每个变频器电路的第一个输入是前一个电路的输出，最后一个变频器电路的输出是锁相环的输入。

公开(公告)号：US07283491B2

公开(公告)日：2007-10-16

申请号：US10281256

申请日：2002-10-28

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H04B7/212

CPC classification number: H04H40/90 ,  H04B7/18582 ,  H04H20/74 ,  H04L12/1836 ,  H04L12/1859 ,  H04L12/189 ,  H04L29/06 ,  H04L67/325 ,  H04L69/329 ,  H04N7/17318 ,  H04N7/20 ,  H04N21/2385 ,  H04N21/47214 ,  H04N21/6143 ,  H04N21/6175

Abstract: In a communication system for carrying out satellite communication through a satellite among users, a satellite communication center is located in a terrestrial network, such as an internet, and has a program table accessible through the terrestrial network and representative of a time schedule of each program to be broadcast through the satellite. The program table can be reserved to broadcast contents by a sender through the internet when an empty time zone is left on the program table. When the reservation is accepted, the contents are sent from the sender through the internet to the satellite communication center and are broadcast at a reserved time through the satellite to other users in accordance with the program table. The contents may be stored in advance in an information storage of the satellite communication center once before they are broadcast or be directly broadcast to the satellite at the reserved time.

Abstract translation: 在用于通过卫星进行卫星通信的通信系统中，卫星通信中心位于诸如互联网的地面网络中，并且具有可通过地面网络访问的节目表，并且代表每个节目的时间表 通过卫星广播。 当节目表上剩下空白时区时，节目表可以由发送者通过互联网预约广播内容。 当预约被接受时，内容通过互联网从发送方发送到卫星通信中心，并且按照节目表通过卫星在保留时间内向其他用户广播。 该内容可以在广播之前预先存储在卫星通信中心的信息存储中，或者在保留时间直接广播到卫星。

公开(公告)号：US07155160B2

公开(公告)日：2006-12-26

申请号：US09835518

申请日：2001-04-17

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H04H1/00

CPC classification number: H04H20/74 ,  H04B7/18584 ,  H04H2201/19 ,  H04N7/17318 ,  H04N21/6143

Abstract: Connected to a satellite earth station for transmitting a broadcast signal to a communication satellite, a data (distribution) center publishes contents of stored information on a home page (HP) of the Internet to submit retrieval of users. When each user determines date to be gotten by retrieving on HP, the user transmits a request signal to the date center via a ground Internet or the communication satellite. Responsive to the request signal, the date center returns a reservation signal including a group address and a distribution scheduled time instant to a request source via the communication satellite. A user's terminal receives date with the group address at a reserved time instant, deciphers the date using a key given from the date center separately, and stores deciphered date in a memory thereof.

Abstract translation: 连接到用于向通信卫星发送广播信号的卫星地球站，数据（分发）中心将存储的信息的内容发布在因特网的主页（HP）上，以提交用户的检索。 当每个用户确定通过在HP上检索获得的日期时，用户经由地面因特网或通信卫星向日期中心发送请求信号。 响应于请求信号，日期中心经由通信卫星将包括组地址和分配预定时刻的预约信号发送到请求源。 用户终端在保留的时刻接收具有组地址的日期，使用从日期中心给出的密钥来解密日期，并将解密的日期存储在其存储器中。

公开(公告)号：US6009313A

公开(公告)日：1999-12-28

申请号：US886954

申请日：1997-07-02

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H04B1/26 ,  H03D7/16 ,  H04B1/40 ,  H04J4/00 ,  H04N5/50

CPC classification number: H03D7/163 ,  H04B1/405

Abstract: A radio communication device includes a transmission carrier generating circuit, a reception intermediate-frequency local signal generating circuit), a transmission radio-frequency local signal generating circuit and a reception radio-frequency local signal generating circuit, each of which is in the form of a frequency synthesizer. The radio communication device further includes a channel connection signal control circuit which cooperatively controls the transmission carrier generating circuit and the transmission radio-frequency local signal generating circuit and cooperatively controls the reception intermediate-frequency local signal generating circuit and the reception radio-frequency local signal generating circuit.

Abstract translation: 无线电通信装置包括：发送载波发生电路，接收中频本地信号发生电路），发送无线电频率本地信号发生电路和接收射频本地信号发生电路，各电路形式为 频率合成器。 无线电通信装置还包括一个信道连接信号控制电路，它协调地控制传输载波发生电路和传输射频本地信号发生电路，并协同控制接收中频本地信号发生电路和接收射频本地信号 发电电路。

公开(公告)号：US5357447A

公开(公告)日：1994-10-18

申请号：US771727

申请日：1991-10-04

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H03L7/08 ,  H03L7/099 ,  H03L7/16 ,  H04L7/00 ,  H04L25/05 ,  G06F7/68 ,  G06F1/04

CPC classification number: H03L7/16 ,  H03L7/0991 ,  H04L25/05 ,  H03L2207/10

Abstract: A first clock signal of fl in frequency is converted into a second clock signal having a frequency of f2=(n/m) f1. The first clock signal is converted by a tank circuit (12) and a converter (13) into an R-bit first phase signal (.theta.1) indicating the phase of the first clock signal. The first phase signal is multiplied by n (mod 2.sup.R) by a multiplier to provide a second phase signal (.theta.3). The second phase signal is supplied to a digital phase-locked loop (PLL) (3) comprising a subtractor (15), a low-pass filter (LPF) (16), a numerically controlled oscillator (NCO) (17) and a multiplier (18). The multiplier in the digital PLL (3) multiplies a third phase signal by m (mod 2.sup.R), indicating the phase of a second clock signal which is the output of the NCO (17), to generate a fourth phase signal. The subtractor (15) generates a signal representing the phase error between the second and fourth phase signals. This phase error signal is filtered by the LPF (16) to control the oscillating phase of the NCO (17). A clock generating circuit generates the second clock signal, on the basis of the third phase signal.

Abstract translation: 频率为f1的第一时钟信号被转换为频率为f2 =（n / m）f1的第二时钟信号。 第一时钟信号由储能电路（12）和转换器（13）转换为指示第一时钟信号的相位的R位第一相位信号（θ1）。 第一相位信号通过乘法乘以n（mod 2R）以提供第二相位信号（θ3）。 第二相位信号被提供给数字锁相环（PLL）（3），包括减法器（15），低通滤波器（LPF）（16），数控振荡器（NCO）（17）和 乘数（18）。 数字PLL（3）中的乘法器将第三相位信号乘以m（mod 2R），指示作为NCO（17）的输出的第二时钟信号的相位，以产生第四相位信号。 减法器（15）产生表示第二和第四相位信号之间的相位误差的信号。 该相位误差信号由LPF（16）滤波，以控制NCO（17）的振荡阶段。 时钟发生电路基于第三相位信号产生第二时钟信号。

公开(公告)号：US5351014A

公开(公告)日：1994-09-27

申请号：US101386

申请日：1993-08-02

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H03L7/197 ,  H03L7/085 ,  H03L7/18 ,  H03L7/16

CPC classification number: H03L7/1806 ,  H03L7/085

Abstract: A frequency synthesizer is composed of a reference oscillator, the first and the second integrators, a binary adder, a low pass filter and VCO forming a Phase Locked Loop (PLL). The first integrator, driven by the timing of a reference oscillator, integrates an externally supplied value K and generates the input signal. The second integrator, driven by the output signal of the VCO of the PLL, integrates an externally supplied value L. The binary adder detects the difference between the outputs of the first and the second integrators functioning as a phase comparator. The output of the phase comparator is converted into an analog voltage which is filtered to control the VCO to achieve frequency synthesis by the phase lock function of the loop.

Abstract translation: 频率合成器由参考振荡器，第一和第二积分器，二进制加法器，低通滤波器和形成锁相环（PLL）的VCO组成。 由参考振荡器的定时驱动的第一个积分器集成了外部提供的值K并产生输入信号。 由PLL的VCO的输出信号驱动的第二积分器对外部提供的值L进行积分。二进制加法器检测用作相位比较器的第一和第二积分器的输出之间的差异。 相位比较器的输出被转换为模拟电压，该模拟电压被滤波以控制VCO，以通过回路的锁相功能实现频率合成。

公开(公告)号：US5268647A

公开(公告)日：1993-12-07

申请号：US947700

申请日：1992-09-21

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H04L27/227 ,  H04L27/00 ,  H04L27/22 ,  H04L27/233 ,  H03D3/00

CPC classification number: H04L27/2332 ,  H04L2027/003 ,  H04L2027/0057 ,  H04L2027/0081

Abstract: In order to coherently demodulate an incoming multi-phase PSK analog signal irrespective of large frequency deviation, an automatic frequency feedback loop is provided. An analog baseband signal is generated by multiplying the IF analog signal by a local signal and then is converted into the corresponding digital baseband signal. A multiplier multiplies the digital baseband signal by another local signal. The output of the multiplier is further multiplied and then applied to a plurality of single-tuned filters which are arranged in parallel and have tuning frequencies each different from an adjacent frequency by a predetermined frequency interval. Each of the plurality of single-tuned filters generates a signal for use in carrier recovery, a frequency error signal and a correlation coefficient. Subsequently, one of the plurality of single-tuned filters is selected in a manner wherein the maximum value is detected among the correlation coefficients. The another local signal is generated using the frequency error signal of the single-tuned filter which has been selected. A modulating signal is reproduced using the recovered carrier in a conventional manner.

公开(公告)号：US4785447A

公开(公告)日：1988-11-15

申请号：US155301

申请日：1988-02-12

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H03H17/02 ,  H04J1/05 ,  H04J4/00

CPC classification number: H04J1/05 ,  H03H17/0213

Abstract: An N-channel FDM signal is converted into complex signals of baseband frequencies spaced at intervals equal to frequency .DELTA.f. The complex baseband signals are converted first into digital samples having a frequency N.DELTA.f and then into N parallel digital signals. A plurality of first FIR subfilters respectively perform filtering on each of the parallel digital signals at frequency .DELTA.f to produce a first series of filtered digital signals from each of the first FIR subfilters, and (m-1) groups of second FIR subfilters respectively perform filtering on each of the parallel digital signals at frequency .DELTA.f to produce a second series of filtered digital samples from each of the second FIR subfilters at timing displaced with respect to the first series by a/m.DELTA.f, where is an integer ranging from unity to (m-1) and m is an integer equal to or greater than 2. Outputs of the first FIR subfilters are combined with outputs of the second FIR subfilters to produce N summation outputs at frequency m.DELTA.f. An N-point Fast Fourier Transform processor performs fast Fourier transform on the N summation outputs at frequency m.DELTA.f to derive digital channels. Because of the oversampling at frequency m.DELTA.f, each of the digital channels has a frequency response which can be made flat over the bandwidth .DELTA.f.

公开(公告)号：US5699383A

公开(公告)日：1997-12-16

申请号：US611557

申请日：1996-03-06

Applicant: Osamu Ichiyoshi

Inventor： Osamu Ichiyoshi

IPC: H03F1/30 ,  H03C3/08 ,  H03F1/32 ,  H04B1/04 ,  H04L27/36 ,  H04B3/08

CPC classification number: H03C3/08 ,  H03F1/3247 ,  H03F1/3294 ,  H04L27/368 ,  H03F2200/102 ,  H03F2201/3233

Abstract: In a high-power transmitter, an input complex signal is multiplied in a complex multiplier by control signals. The output complex signal from the multiplier is converted to a high frequency signal and amplified by a power amplifier for transmission. The amplitude of the input complex signal is detected to access a memory where amplitude and phase correction values are stored. During a read mode of the memory, a set of amplitude and phase correction values is specified by the detected amplitude and supplied to the complex amplifier as the control signals. During a write mode of the memory, a set of amplitude and phase correction values is specified by a delayed version of the detected amplitude and rewritten with a set of new amplitude and phase correction values. The amplified high frequency signal is down-converted to a low frequency complex signal. The nonlinearity of the power amplifier is determined from a delayed version of the input complex signal and the down-converted complex signal and the new amplitude and phase correction values are produced from the detected nonlinearity and delayed versions of the amplitude and phase correction values which were supplied to the complex multiplier. At intervals, the memory is switched from the read mode to the write mode for updating its contents.

Abstract translation: 在大功率发射机中，输入复信号通过控制信号在复数乘法器中相乘。 来自乘法器的输出复信号被转换为高频信号并由功率放大器放大以用于传输。 检测输入复信号的幅度以访问存储振幅和相位校正值的存储器。 在存储器的读取模式期间，通过检测到的幅度指定一组幅度和相位校正值，并将其提供给复数放大器作为控制信号。 在存储器的写入模式期间，一组幅度和相位校正值由检测到的幅度的延迟版本指定并用一组新的幅度和相位校正值重写。 放大的高频信号被下变频成低频复信号。 功率放大器的非线性由输入复合信号和下变频复信号的延迟版本确定，新的幅度和相位校正值由检测到的非线性和幅度和相位校正值的延迟版本产生，幅度和相位校正值是 提供给复数乘法器。 间隔地，存储器从读取模式切换到用于更新其内容的写入模式。