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公开(公告)号：US20080016141A1
公开(公告)日：2008-01-17
申请号：US11457380
申请日：2006-07-13
IPC分类号： G06G7/16
CPC分类号： G06G7/26
摘要： A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents.
摘要翻译： 直接数字合成电路（108）包括多个电流源（210,211,212），输出电路（200）和逻辑乘法器电路（202）。 输出电路（200）提供输出的合成波形（164），并包括第一分支（206）和第二分支（208）。 逻辑乘法器电路（202）可操作地耦合到多个电流源（210,211,212）和输出电路（200）。 逻辑乘法器电路（202）可操作以接收多个信号。 逻辑乘法器电路还可操作以选择性地将通过第一分支（206）的第一电流流动增加确定的幅度，并且基于多个信号减少通过第二分支（208）的确定的幅度的第二电流。 合成波形（164）基于第一和第二电流。
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12.发明授权Method and apparatus for selectively activating radio frequency identification tags that are in close proximity 有权用于选择性地激活非常接近的射频识别标签的方法和装置公开(公告)号：US06392544B1
公开(公告)日：2002-05-21
申请号：US09669289
申请日：2000-09-25
IPC分类号： G08B1314
CPC分类号： G06K7/10346 , G06K7/0008 , G06K7/10019 , G06K7/10316
摘要： A radio frequency identification exciter (200) includes a plurality of antenna elements (122a-i) that are spaced to define active areas (130a-e). A matrix switch (202) flexibly connects the plurality of antenna elements to an exciter circuit (203). Independent switches (204a-i) are selectively switched such that an electric field is generated between at least two antenna elements whereby radio frequency identification tags (132) in the vicinity of the two antenna elements are capacitively powered to exchange data with the exciter. Antenna elements other than the at least two antenna elements may be selectively coupled to a signal from the exciter circuit that inhibits activation of radio frequency identification tags in the vicinity of those antenna elements. The matrix switch preferably comprises polymer-based circuits.
摘要翻译： 射频识别激励器（200）包括间隔开以限定有源区域（130a-e）的多个天线元件（122a-i）。 矩阵开关（202）将多个天线元件灵活地连接到激励器电路（203）。 选择性地切换独立开关（204a-i），使得在至少两个天线元件之间产生电场，由此在两个天线元件附近的射频识别标签（132）被电容地供电以与激励器交换数据。 除了至少两个天线元件之外的天线元件可以选择性地耦合到来自激励器电路的信号，该信号禁止在那些天线元件附近激活射频识别标签。 矩阵开关优选地包括基于聚合物的电路。
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公开(公告)号：US06384727B1
公开(公告)日：2002-05-07
申请号：US09630987
申请日：2000-08-02
IPC分类号： G08B1314
CPC分类号： H01Q1/2225 , G06F19/00 , G06K19/077 , G06K19/07749 , H01Q9/285 , H01Q23/00 , Y10T29/49155
摘要： A capacitively powered radio frequency identification device (10) comprises a substrate (12), a conductive pattern (14, 16) and a circuit (18). The substrate (12) has a first surface and a second surface. The conductive pattern is formed on the first surface of the substrate (12). The conductive pattern has a first electrode (14) and a second electrode (16). The first and second electrodes (14, 16) are isolated from each other by a non-conductive region disposed therebetween. The circuit (18) comprises polymers. The circuit (18) is electrically coupled to the first electrode (14) and the second electrode (16).
摘要翻译： 电容供电的射频识别装置（10）包括基板（12），导电图案（14,16）和电路（18）。 衬底（12）具有第一表面和第二表面。 导电图案形成在基板（12）的第一表面上。 导电图案具有第一电极（14）和第二电极（16）。 第一和第二电极（14,16）通过设置在它们之间的非导电区域彼此隔离。 电路（18）包括聚合物。 电路（18）电耦合到第一电极（14）和第二电极（16）。
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公开(公告)号：US5894284A
公开(公告)日：1999-04-13
申请号：US753812
申请日：1996-12-02
CPC分类号： H03F3/005 , H03F3/45479 , H03M1/442
摘要： A common-mode sensing circuit (504) of a clocked differential amplifier (602) includes a refresh circuit (604) which precharges a capacitance during a first clock phase (P.sub.1) and discharges the capacitance to drive the outputs (514, 516) of the differential amplifier (602) to a desired common-mode voltage (V.sub.AGO) during a second clock phase, which increases the output loading during the second clock phase (P.sub.2). A load balancing circuit (606) selectively switches a load to the outputs (514, 516) during the first clock phase (P.sub.1) to match the load produced by the refresh circuit (604) during the second clock phase (P.sub.2).
摘要翻译： 时钟差分放大器（602）的共模感测电路（504）包括刷新电路（604），其在第一时钟相位（P1）期间对电容进行预充电，并且将电容放电以驱动输出（514,516）的 差分放大器（602）在第二时钟相位期间达到期望的共模电压（VAGO），这增加了在第二时钟相位（P2）期间的输出负载。 负载平衡电路（606）在第一时钟相位（P1）期间选择性地将负载切换到输出（514,516）以匹配在第二时钟相位（P2）期间由刷新电路（604）产生的负载。
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公开(公告)号：US5818276A
公开(公告)日：1998-10-06
申请号：US610178
申请日：1996-03-04
CPC分类号： H03K5/1515
摘要： A non-inverting, inverting, delayed non-inverting, and delayed inverting non-overlapping clock signal is provided by a non-overlapping clock generator circuit (41, 61). The non-overlapping clock generator circuit (41, 61) increases time for circuit operation by minimizing delays between non-overlapping clock signals and simultaneously transitioning rising edges of clock signals. A non-overlapping clock generation circuit (41) comprises six NOR gates (43-48) and an inverter (42). Three NOR gates form a first delay line (43-45) and the remaining three NOR gates form a second delay line (46-48). The inverter (42) provides an inverted clock signal to the second delay line. A clock signal propagates through one delay line while the other delay line is non-responsive due to a feedback signal from the active delay line. Once the clock signal has propagated through the active delay line, the feedback signal changes and allows NOR gates of the remaining delay line to simultaneously provide a clock signal and a delayed clock signal.
摘要翻译： 由非重叠时钟发生器电路（41,61）提供非反相，反相，延迟的非反相和延迟的反相非重叠时钟信号。 不重叠的时钟发生器电路（41,61）通过最小化不重叠的时钟信号之间的延迟并同时转换时钟信号的上升沿来增加电路操作的时间。 非重叠时钟产生电路（41）包括六个或非门（43-48）和一个反相器（42）。 三个或非门形成第一延迟线（43-45），其余三个或非门形成第二延迟线（46-48）。 反相器（42）向第二延迟线提供反相时钟信号。 时钟信号通过一个延迟线传播，而另一个延迟线由于来自有源延迟线的反馈信号而不响应。 一旦时钟信号已经通过有源延迟线传播，反馈信号改变并允许剩余延迟线的“或非”门同时提供时钟信号和延迟的时钟信号。
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公开(公告)号：US5574457A
公开(公告)日：1996-11-12
申请号：US489349
申请日：1995-06-12
CPC分类号： H03M1/442 , H03F3/005 , H03H19/004
摘要： A switched capacitor gain stage (21) that samples an input voltage every clock cycle phase for effectively doubling the frequency of operation. The switched capacitor gain stage (21) comprising an amplifier (22), a first capacitor network, and a second capacitor network. Either the first or second capacitor network is sampling an input voltage. For example, the first capacitor network samples an input voltage. Capacitors of the first capacitor network are coupled to sample the input voltage via switches. Capacitors of the second switched capacitor network are coupled around the amplifier (22) in a gain configuration via switches. The capacitors of the second switched capacitor network having a voltage stored from a previous clock phase. In a next clock phase the second switched capacitor network are coupled via switches for sampling an input voltage and the first switched capacitor network is coupled via switches in a gain configuration around the amplifier (22).
摘要翻译： 开关电容器增益级（21），每个时钟周期阶段对输入电压进行采样，以有效地加倍工作频率。 开关电容器增益级（21）包括放大器（22），第一电容器网络和第二电容器网络。 第一或第二电容器网络都要对输入电压进行采样。 例如，第一电容器网络对输入电压进行采样。 第一电容器网络的电容器被耦合以通过开关对输入电压进行采样。 第二开关电容器网络的电容器通过开关以增益配置耦合在放大器（22）周围。 第二开关电容器网络的电容器具有从先前时钟相位存储的电压。 在下一个时钟阶段，第二开关电容器网络通过用于对输入电压进行采样的开关耦合，并且第一开关电容器网络通过放大器（22）周围的增益配置的开关耦合。
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17.发明授权Differential transmission line shielded by two or more spaced groups of shields 有权差分传输线由两个或更多间隔的屏蔽组屏蔽公开(公告)号：US08922291B2
公开(公告)日：2014-12-30
申请号：US13467447
申请日：2012-05-09
申请人： Haolu Xie , Chi-Taou Tsai , Patrick L. Rakers
发明人： Haolu Xie , Chi-Taou Tsai , Patrick L. Rakers
IPC分类号： H05K1/02
CPC分类号： H05K1/0219 , H01L23/5225 , H01L2924/0002 , H01P3/02 , H01R13/6461 , H05K1/0245 , Y10T29/49117 , H01L2924/00
摘要： A shield for differential transmission lines formed in a first metal layer may include one or more floating shields, each floating shield comprising an upper-side tile formed in a second metal layer of the integrated circuit adjacent to the first metal layer, a lower-side tile formed in a third metal layer of the integrated circuit adjacent to the first metal layer and non-adjacent to the second metal layer, and at least one via configured to electrically couple the upper-side tile at an end of the length of the upper-side tile to the lower-side tile and at an end of the length of the lower-side tile.
摘要翻译： 形成在第一金属层中的差分传输线的屏蔽可以包括一个或多个浮动屏蔽，每个浮动屏蔽包括形成在与第一金属层相邻的集成电路的第二金属层中的上侧瓦，下侧 在与所述第一金属层相邻并且不与所述第二金属层相邻的所述集成电路的第三金属层中形成的至少一个通孔，以及至少一个通孔，其构造成在所述上部的所述长度的末端的末端电连接所述上侧瓦 并且在下侧瓦片的长度的末端。
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公开(公告)号：US20130300514A1
公开(公告)日：2013-11-14
申请号：US13467447
申请日：2012-05-09
申请人： Haolu Xie , Chi-Taou Tsai , Patrick L. Rakers
发明人： Haolu Xie , Chi-Taou Tsai , Patrick L. Rakers
CPC分类号： H05K1/0219 , H01L23/5225 , H01L2924/0002 , H01P3/02 , H01R13/6461 , H05K1/0245 , Y10T29/49117 , H01L2924/00
摘要： A shield for differential transmission lines formed in a first metal layer may include one or more floating shields, each floating shield comprising an upper-side tile formed in a second metal layer of the integrated circuit adjacent to the first metal layer, a lower-side tile formed in a third metal layer of the integrated circuit adjacent to the first metal layer and non-adjacent to the second metal layer, and at least one via configured to electrically couple the upper-side tile at an end of the length of the upper-side tile to the lower-side tile and at an end of the length of the lower-side tile.
摘要翻译： 形成在第一金属层中的差分传输线的屏蔽可以包括一个或多个浮动屏蔽，每个浮动屏蔽包括形成在与第一金属层相邻的集成电路的第二金属层中的上侧瓦，下侧 在与所述第一金属层相邻并且不与所述第二金属层相邻的所述集成电路的第三金属层中形成的至少一个通孔，以及至少一个通孔，其构造成在所述上部的所述长度的末端的末端电连接所述上侧瓦 并且在下侧瓦片的长度的末端。
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公开(公告)号：US20130194116A1
公开(公告)日：2013-08-01
申请号：US13363884
申请日：2012-02-01
申请人： Omid Oliaei , Patrick L. Rakers
发明人： Omid Oliaei , Patrick L. Rakers
摘要： In accordance with embodiments of the present disclosure, a continuous-time incremental analog-to-digital converter (ADC) may include a plurality of resettable integrators and a feed-in gain element. Each integrator may be configured to convert a sum of signals received at its input to a signal indicative of an integral over time of the sum of signals. The plurality of integrators may include a first-stage integrator configured to receive at its input the baseband signal and a final-stage integrator configured to produce at its output a final-stage analog signal. The plurality of integrators may be arranged in a cascade configuration such that an output of each of the plurality of integrators other than the final-stage integrator is coupled to the input of a subsequent integrator. The feed-in gain element may be coupled between the input of the first-stage integrator and the input of another integrator of the plurality of integrators.
摘要翻译： 根据本公开的实施例，连续时间增量模数转换器（ADC）可以包括多个可复位积分器和馈入增益元件。 每个积分器可以被配置为将在其输入处接收的信号的和转换成指示信号总和的积分的信号。 多个积分器可以包括被配置为在其输入处接收基带信号的第一级积分器和被配置为在其输出端产生最终级模拟信号的最终级积分器。 多个积分器可以被布置成级联配置，使得除了最终级积分器之外的多个积分器中的每一个的输出耦合到后续积分器的输入。 馈入增益元件可以耦合在第一级积分器的输入端和多个积分器的另一个积分器的输入端之间。
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公开(公告)号：US20130039438A1
公开(公告)日：2013-02-14
申请号：US13207786
申请日：2011-08-11
IPC分类号： H04L27/00
CPC分类号： H03D7/1441 , H03D7/1458 , H03D2200/0023 , H04B1/0057 , H04B1/0483
摘要： In accordance with some embodiments of the present disclosure, a multi-band transmitter comprises a plurality of band paths with each band path configured for a different frequency range. Each band path comprises a modulator configured to modulate a data signal onto a carrier signal associated with the frequency range of the band path to generate a radio frequency (RF) signal associated with the band path and frequency range of the band path. Each band path also comprises a step-down balun that includes an input coil configured to receive the RF signal from the modulator. Each band path further comprises a tuner configured to tune the input coil to the frequency range of the band path. The tuner is also configured to compensate for off-state conduction of switches of the tuner to reduce non-linear tuning effects of the balun associated with the off-state conduction.
摘要翻译： 根据本公开的一些实施例，多频带发射机包括多个频带路径，每个频带路径被配置用于不同的频率范围。 每个频带路径包括被配置为将数据信号调制到与频带路径的频率范围相关联的载波信号上以产生与频带路径的频带路径和频带范围相关联的射频（RF）信号的调制器。 每个频带路径还包括降压平衡 - 不平衡变压器，其包括被配置为从调制器接收RF信号的输入线圈。 每个频带路径还包括被配置为将输入线圈调谐到频带路径的频率范围的调谐器。 调谐器还被配置为补偿调谐器的开关的截止状态传导，以减少与断开状态传导相关联的平衡 - 不平衡变换器的非线性调谐效应。
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