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12 条记录 (耗时 0.011 秒)

    Limiting parasitic signal coupling between conductors
    2.
    发明授权
    Limiting parasitic signal coupling between conductors 失效
    限制导体之间的寄生信号耦合

    公开(公告)号：US5243547A

    公开(公告)日：1993-09-07

    申请号：US862015

    申请日：1992-04-01

    申请人： Chi-Taou Tsai ,  Wai-Yeung Yip

    发明人： Chi-Taou Tsai ,  Wai-Yeung Yip

    IPC分类号： G06F17/50 ,  H05K1/02 ,  H05K3/00

    CPC分类号： H05K3/0005 ,  G06F17/5036 ,  G06F2217/40 ,  H05K1/0216 ,  H05K1/0228 ,  H05K1/0292 ,  H05K2201/09236

    摘要： A plurality of conductors (10, 11, 12, 15) are formed into sections (13, 14, 16, 17, 18, 19) having uniform cross-sectional area. Per unit electrical parameters are developed for each section (13, 14, 16, 17, 18, 19). A conductor of the plurality of conductors (10, 11, 12, 15) is partitioned into a number of equal length segments. All other conductors are partitioned into the same number of segments. For each segment, a lumped element model (24, 26, 28, 29) is developed. The model (24, 26, 28, 29) includes a capacitor (33), an inductor (32), a plurality of mutual inductors (36, 38, 31), and a plurality of mutual capacitors (37, 39, 40). Each model (24, 26, 28, 29) of a conductor (10, 11, 12, 15) is serially connected to provide an equivalent circuit (23, 27) of each conductor (10, 11, 12, 15). The circuits (23, 27) are simulated to determine the amount of signal coupling. The conductors (10, 11, 12, 15) are then modified to limit the signal coupling to desired values, and the procedure is repeated.

    摘要翻译： 多个导体（10,11,12,15）形成为具有均匀横截面面积的部分（13,14,16,17,18,19）。 对于每个部分（13,14,16,17,18,19）开发每单位电参数。 多个导体（10,11,12,15）的导体被划分成多个相等长度的片段。 所有其他导体被划分成相同数量的片段。 对于每个段，开发了集总元件模型（24,26,28,29）。 该模型（24,26,28,29）包括电容器（33），电感器（32），多个互感器（36,38,31）和多个互电容器（37,39,40） 。 导体（10,11,12,15）的每个型号（24,26,28,29）被串联连接以提供每个导体（10,11,12,15）的等效电路（23,27）。 模拟电路（23,27）以确定信号耦合的量。 然后修改导体（10,11,12,15）以将信号耦合到期望值，并重复该过程。

    Differential transmission line shielded by two or more spaced groups of shields
    3.
    发明授权
    Differential transmission line shielded by two or more spaced groups of shields 有权
    差分传输线由两个或更多间隔的屏蔽组屏蔽

    公开(公告)号：US08922291B2

    公开(公告)日：2014-12-30

    申请号：US13467447

    申请日：2012-05-09

    申请人： Haolu Xie ,  Chi-Taou Tsai ,  Patrick L. Rakers

    发明人： Haolu Xie ,  Chi-Taou Tsai ,  Patrick L. Rakers

    IPC分类号： H05K1/02

    CPC分类号： H05K1/0219 ,  H01L23/5225 ,  H01L2924/0002 ,  H01P3/02 ,  H01R13/6461 ,  H05K1/0245 ,  Y10T29/49117 ,  H01L2924/00

    摘要： A shield for differential transmission lines formed in a first metal layer may include one or more floating shields, each floating shield comprising an upper-side tile formed in a second metal layer of the integrated circuit adjacent to the first metal layer, a lower-side tile formed in a third metal layer of the integrated circuit adjacent to the first metal layer and non-adjacent to the second metal layer, and at least one via configured to electrically couple the upper-side tile at an end of the length of the upper-side tile to the lower-side tile and at an end of the length of the lower-side tile.

    摘要翻译： 形成在第一金属层中的差分传输线的屏蔽可以包括一个或多个浮动屏蔽，每个浮动屏蔽包括形成在与第一金属层相邻的集成电路的第二金属层中的上侧瓦，下侧 在与所述第一金属层相邻并且不与所述第二金属层相邻的所述集成电路的第三金属层中形成的至少一个通孔，以及至少一个通孔，其构造成在所述上部的所述长度的末端的末端电连接所述上侧瓦 并且在下侧瓦片的长度的末端。

    Transmission Line Shielding
    4.
    发明申请
    Transmission Line Shielding 有权
    传输线屏蔽

    公开(公告)号：US20130300514A1

    公开(公告)日：2013-11-14

    申请号：US13467447

    申请日：2012-05-09

    申请人： Haolu Xie ,  Chi-Taou Tsai ,  Patrick L. Rakers

    发明人： Haolu Xie ,  Chi-Taou Tsai ,  Patrick L. Rakers

    IPC分类号： H01P3/08 ,  H05K9/00 ,  H01R43/00

    CPC分类号： H05K1/0219 ,  H01L23/5225 ,  H01L2924/0002 ,  H01P3/02 ,  H01R13/6461 ,  H05K1/0245 ,  Y10T29/49117 ,  H01L2924/00

    摘要： A shield for differential transmission lines formed in a first metal layer may include one or more floating shields, each floating shield comprising an upper-side tile formed in a second metal layer of the integrated circuit adjacent to the first metal layer, a lower-side tile formed in a third metal layer of the integrated circuit adjacent to the first metal layer and non-adjacent to the second metal layer, and at least one via configured to electrically couple the upper-side tile at an end of the length of the upper-side tile to the lower-side tile and at an end of the length of the lower-side tile.

    摘要翻译： 形成在第一金属层中的差分传输线的屏蔽可以包括一个或多个浮动屏蔽，每个浮动屏蔽包括形成在与第一金属层相邻的集成电路的第二金属层中的上侧瓦，下侧 在与所述第一金属层相邻并且不与所述第二金属层相邻的所述集成电路的第三金属层中形成的至少一个通孔，以及至少一个通孔，其构造成在所述上部的所述长度的末端的末端电连接所述上侧瓦 并且在下侧瓦片的长度的末端。

    Applications of a high impedance surface
    6.
    发明授权
    Applications of a high impedance surface 有权
    高阻抗表面的应用

    公开(公告)号：US07136028B2

    公开(公告)日：2006-11-14

    申请号：US10927921

    申请日：2004-08-27

    申请人： Ramamurthy Ramprasad ,  Michael F. Petras ,  Chi Taou Tsai

    发明人： Ramamurthy Ramprasad ,  Michael F. Petras ,  Chi Taou Tsai

    IPC分类号： H01Q15/02

    CPC分类号： H01Q15/008

    摘要： Disclosed herein are various high-impedance surfaces having high capacitance and inductance properties and methods for their manufacture. One exemplary high-impedance surface includes a plurality of conductive structures arranged in a lattice, wherein at least a subset of the conductive structures include a plurality of conductive plates arranged along a conductive post so that the conductive plates of one conductive structure interleave with one or more conductive plates of one or more adjacent conductive structure. Another exemplary high-impedance surface includes a plurality of conductive structures arranged in a lattice, where the conductive structures include one or more fractalized conductive plates having either indentions and/or projections that are coextensive with corresponding projections or indentations, respectively, of one or more adjacent conductive structures. Also disclosed are various exemplary implementations of such high-impedance surfaces.

    摘要翻译： 本文公开了具有高电容和电感特性的各种高阻抗表面及其制造方法。 一个示例性的高阻抗表面包括布置成格子的多个导电结构，其中导电结构的至少一个子集包括沿着导电柱布置的多个导电板，使得一个导电结构的导电板与一个或多个导电结构交错 一个或多个相邻导电结构的更多导电板。 另一个示例性的高阻抗表面包括以格子布置的多个导电结构，其中导电结构包括一个或多个分形导电板，其具有与一个或多个相应的相应突起或凹部共同延伸的凹陷和/或突起 相邻的导电结构。 还公开了这种高阻抗表面的各种示例性实施方式。

    Method for automatic tab artwork building
    7.
    发明授权
    Method for automatic tab artwork building 失效
    自动标签图形构建方法

    公开(公告)号：US5465217A

    公开(公告)日：1995-11-07

    申请号：US106852

    申请日：1993-08-16

    申请人： Wai-Yeung Yip ,  Arijit Chandra ,  Chi-Taou Tsai

    发明人： Wai-Yeung Yip ,  Arijit Chandra ,  Chi-Taou Tsai

    IPC分类号： G06F17/50 ,  H01L23/498 ,  H01L23/48

    CPC分类号： G06F17/5068 ,  H01L23/49838 ,  H01L2924/0002

    摘要： A method for automated artwork building which comprises determining a desired die pad pitch, assigning inner lead bonding positions for each lead based on the average die pitch. The desired outer lead bonding position is then determined for each lead. The allowable range of fan in and fan out angles for each lead is computed according to design and manufacturing constraints. An electrical cost function is formulated based on signal lead crosstalk and ground lead simultaneous switching noise. Each lead is then routed. The routing is repeated for each lead for each allowable combination of fan in and fan out angles. Finally the optimal routing is selected based on electrical characteristics.

    摘要翻译： 一种用于自动化图形构建的方法，包括确定期望的管芯焊盘间距，基于平均管芯间距为每个引线分配内引线接合位置。 然后为每个引线确定所需的外部引线键合位置。 根据设计和制造限制计算每个引线的风扇进风扇和风扇角度的允许范围。 基于信号引线串扰和接地引线同时开关噪声来制定电气成本函数。 然后每个引线被路由。 对于每个允许的风扇和扇出角度的组合，每个引线重复布线。 最后，根据电气特性选择最优路由。

    Providing a PGA package with a low reflection line
    8.
    发明授权
    Providing a PGA package with a low reflection line 失效
    提供具有低反射线的PGA封装

    公开(公告)号：US5012213A

    公开(公告)日：1991-04-30

    申请号：US452488

    申请日：1989-12-19

    申请人： Chi-Taou Tsai

    发明人： Chi-Taou Tsai

    IPC分类号： H01L23/66

    CPC分类号： H01L23/66 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011

    摘要： A conventional pin grid array package is provided with microwave frequency signal lines by wire bonding two adjacent conductive lines together. The wire bonding process is done at the same time that a semiconductor device is electrically connected to the pin grid array package. The two adjacent wire bonded conductive lines will have very low reflection or signal loss and therefore can be used with signals having a fast rise time or fast edge rates. The wire bond connection does not significantly degrade a constant impedance line for the signal.

    摘要翻译： 常规的针阵阵列封装通过将两个相邻的导线连接在一起而提供有微波频率信号线。 引线接合工艺在半导体器件电连接到引脚栅极阵列封装的同时进行。 两个相邻引线键合的导线将具有非常低的反射或信号损耗，因此可以与具有快速上升时间或快速边沿速率的信号一起使用。 引线键合连接不会显着降低信号的恒定阻抗线。

    Frequency selective high impedance surface
    10.
    发明授权
    Frequency selective high impedance surface 有权

    公开(公告)号：US07136029B2

    公开(公告)日：2006-11-14

    申请号：US10927944

    申请日：2004-08-27

    申请人： Ramamurthy Ramprasad ,  Michael F. Petras ,  Chi Taou Tsai

    发明人： Ramamurthy Ramprasad ,  Michael F. Petras ,  Chi Taou Tsai

    IPC分类号： H01Q15/02 ,  H01Q1/38

    CPC分类号： H01Q15/008 ,  H01Q1/22 ,  H01Q1/48

    摘要： Disclosed herein are various high-impedance surfaces having high capacitance and inductance properties. One exemplary high-impedance surface includes a plurality of conductive structures arranged in a lattice, wherein at least a subset of the conductive structures include a plurality of conductive plates arranged along a conductive post so that the conductive plates of one conductive structure interleave with one or more conductive plates of one or more adjacent conductive structure. Another exemplary high-impedance surface includes a plurality of conductive structures arranged in a lattice, where the conductive structures include one or more fractalized conductive plates having either indentions and/or projections that are coextensive with corresponding projections or indentations, respectively, of one or more adjacent conductive structures. Also disclosed are various exemplary implementations of such high-impedance surfaces.