公开(公告)号：US20060291263A1

公开(公告)日：2006-12-28

申请号：US11128789

申请日：2005-05-13

申请人： Paul Wallner ,  Ralf Schledz ,  Peter Gregorius ,  Hermann Ruckerbauer

发明人： Paul Wallner ,  Ralf Schledz ,  Peter Gregorius ,  Hermann Ruckerbauer

IPC分类号： G11C5/06

CPC分类号： G11C5/063

摘要： A memory system and method is disclosed. In one embodiment, the memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.

摘要翻译： 公开了一种存储器系统和方法。 在一个实施例中，存储器系统包括存储器控制器和至少一个存储器模块，其中一定数量的半导体存储器芯片和连接线被布置在分别指定的拓扑中。 连接线包括形成传输通道的第一连接线，用于基于协议的数据传输和命令信号流从存储器控制器分别存储到存储器模块上的存储器芯片和存储器控制器中的至少一个。 将第二连接线从存储器控制器直接路由到存储器模块上的至少一个存储器芯片，用于将选择信息与数据和命令信号流分离地传送到至少一个存储器芯片。

公开(公告)号：US20060193414A1

公开(公告)日：2006-08-31

申请号：US11345668

申请日：2006-02-02

申请人： Peter Gregorius ,  Paul Wallner

发明人： Peter Gregorius ,  Paul Wallner

IPC分类号： H04L7/00

CPC分类号： H03L7/091 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03L7/0814 ,  H04L7/0337

摘要： A synchronization and data recovery device (SuD) for clock-synchronized recovery of data bits in a data stream is provided, which is particularly suitable for improved backward identification of data in serial receiver interfaces of high-speed semiconductor memory modules and/or memory controller modules with a low data density. The SuD includes a sampling unit, a data adjustment unit, a digital monitoring unit, a phase lock detector unit, a phase generator, an FIR low-pass filter and a data recovery decision unit. After synchronization of the values that have been sampled by the sampling unit in the data adjustment unit, these values are filtered in the FIR low-pass filter unit, which indicates a greater tolerance with respect to fluctuations in the ideal sampling time, in that it uses sample values of the previous symbol and of the subsequent symbol in addition to the sample values of the symbol to be identified.

摘要翻译： 提供了用于数据流中数据位的时钟同步恢复的同步和数据恢复设备（SuD），其特别适用于改进高速半导体存储器模块和/或存储器控制器的串行接收器接口中数据的向后标识 具有低数据密度的模块。 SuD包括采样单元，数据调整单元，数字监视单元，锁相检测器单元，相位发生器，FIR低通滤波器和数据恢复判定单元。 在由数据调整单元中的采样单元采样的值同步之后，这些值在FIR低通滤波器单元中被滤波，这表示相对于理想采样时间的波动具有更大的公差，因为它 除了要识别的符号的样本值之外，还使用先前符号和后续符号的采样值。

公开(公告)号：US20060104132A1

公开(公告)日：2006-05-18

申请号：US10986767

申请日：2004-11-15

申请人： Hermann Ruckerbauer ,  Dominique Savignac ,  Christian Sichert ,  Peter Gregorius ,  Paul Wallner

发明人： Hermann Ruckerbauer ,  Dominique Savignac ,  Christian Sichert ,  Peter Gregorius ,  Paul Wallner

IPC分类号： G11C7/00

CPC分类号： G11C7/1045 ,  G11C5/04 ,  G11C7/1018

摘要： A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst length. The system is characterized in that a number of additional bits extending the burst length are transferred together with at least every nth signal burst.

摘要翻译： 用于在接口电路之间传送写入和读取数据信号的半导体存储器系统包括至少一个存储器件，存储器控制器单元和可选地半导体存储器系统的寄存器单元，其中数据信号各自以信号脉冲串 具体的突发长度。 该系统的特征在于，延伸突发长度的多个附加位与至少每个第n个信号脉冲串一起传送。

公开(公告)号：US07663964B2

公开(公告)日：2010-02-16

申请号：US11735971

申请日：2007-04-16

申请人： Paul Wallner ,  Peter Gregorius

发明人： Paul Wallner ,  Peter Gregorius

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： A memory device including a memory cell array; an input circuit providing drive signals to the memory cell array dependent on externally received command data; an output buffer buffering data read out from the memory cell array; and a timer driving the output buffer such that the buffered data are provided at an output after an adjustable time interval has elapsed, the adjustable time interval beginning with the provision of the drive signals.

摘要翻译： 一种包括存储单元阵列的存储器件; 输入电路，其根据外部接收到的命令数据向存储单元阵列提供驱动信号; 缓冲从存储单元阵列读出的数据的输出缓冲器; 以及驱动输出缓冲器的定时器，使得缓冲的数据在经过可调整时间间隔之后的输出处提供，可调整的时间间隔从提供驱动信号开始。

公开(公告)号：US07475187B2

公开(公告)日：2009-01-06

申请号：US11226457

申请日：2005-09-15

申请人： Peter Gregorius ,  Hermann Ruckerbauer ,  Paul Wallner

发明人： Peter Gregorius ,  Hermann Ruckerbauer ,  Paul Wallner

IPC分类号： G06F15/17

CPC分类号： G11C7/1006 ,  G11C2207/107 ,  H03M9/00

摘要： In a semiconductor memory system, the memory chips are linked to a memory module in a shared loop forward architecture and connected in a point-to-point connection to a memory controller. Each memory chip includes a high-speed interface circuit including: a read and write data/command-and-address signal re-driver/transmitter path for re-driving serial read data and write data/command-and-address signals not destined for the semiconductor memory chip; and a main signal path which includes a serial-to-parallel converter and a synchronizer for serial-to-parallel converting and synchronizing with a reference clock signal write data/command-and-address signals destined for the semiconductor memory chip as well as a parallel-to-serial converter for parallel-to-serial converting read data signals read from a memory core of the memory chips, and a switch for inserting the parallel-to-serial converted read data signals into the re-driver/transmitter path. Optionally the high-speed interface circuit additionally includes a transparent re-driver/transmitter path not including any synchronizing circuitry.

摘要翻译： 在半导体存储器系统中，存储器芯片被链接到共享回路前向架构中的存储器模块，并且以点对点连接连接到存储器控制器。 每个存储器芯片包括一个高速接口电路，包括：用于重新驱动串行读取数据的读取和写入数据/命令和地址信号重新驱动器/发送器路径，并且写入不预定的数据/命令和地址信号 半导体存储芯片; 以及主信号路径，其包括串行到并行转换器和用于串行到并行转换并与参考时钟信号同步的同步器，写入用于半导体存储器芯片的数据/命令和地址信号以及一个 并行到串行转换器，用于并行到串行转换从存储器芯片的存储器核心读取的读取数据信号，以及用于将并行到串行转换的读取数据信号插入重新驱动器/发送器路径的开关。 可选地，高速接口电路还包括不包括任何同步电路的透明重新驱动器/发射器路径。

公开(公告)号：US20080229033A1

公开(公告)日：2008-09-18

申请号：US11686818

申请日：2007-03-15

申请人： Paul Wallner ,  Peter Gregorius

发明人： Paul Wallner ,  Peter Gregorius

IPC分类号： G06F12/00

CPC分类号： G11C7/10 ,  G11C7/1006

摘要： A method processes data in a memory arrangement. The method includes receiving and transmitting the data from the memory arrangement in the form of data packets according to a predefined protocol. The method includes distributing each received data packet to at least two separate data packet processing units. Each data packet processing unit is coupled to a portion of memory cells of the memory arrangement. The method includes processing, at each data packet processing unit, parts of the received data packets that relate to the portion of the memory cells the data packet processing unit is coupled to. The method includes generating a data packet to be transmitted including setting up, with each data packet processing unit, a part of the data packet to be transmitted.

摘要翻译： 一种方法处理存储器装置中的数据。 该方法包括根据预定义的协议以数据分组的形式接收和发送来自存储器装置的数据。 该方法包括将每个接收到的数据分组分发到至少两个单独的数据分组处理单元。 每个数据分组处理单元耦合到存储器装置的存储单元的一部分。 该方法包括在每个数据分组处理单元处处理与数据分组处理单元耦合的存储单元部分相关的接收数据分组的部分。 该方法包括生成要发送的数据分组，包括与每个数据分组处理单元一起建立要发送的数据分组的一部分。

公开(公告)号：US07339840B2

公开(公告)日：2008-03-04

申请号：US11128789

申请日：2005-05-13

申请人： Paul Wallner ,  Ralf Schledz ,  Peter Gregorius ,  Hermann Ruckerbauer

发明人： Paul Wallner ,  Ralf Schledz ,  Peter Gregorius ,  Hermann Ruckerbauer

IPC分类号： G11C7/00

CPC分类号： G11C5/063

摘要： A memory system and method is discussed. The memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.

摘要翻译： 讨论了存储器系统和方法。 存储器系统包括存储器控制器和至少一个存储器模块，其中一定数量的半导体存储器芯片和连接线路布置在分别指定的拓扑中。 连接线包括形成传输通道的第一连接线，用于基于协议的数据传输和命令信号流从存储器控制器分别存储到存储器模块上的存储器芯片和存储器控制器中的至少一个。 将第二连接线从存储器控制器直接路由到存储器模块上的至少一个存储器芯片，用于将选择信息与数据和命令信号流分离地传送到至少一个存储器芯片。

公开(公告)号：US20070073942A1

公开(公告)日：2007-03-29

申请号：US11226457

申请日：2005-09-15

申请人： Peter Gregorius ,  Hermann Ruckerbauer ,  Paul Wallner

发明人： Peter Gregorius ,  Hermann Ruckerbauer ,  Paul Wallner

IPC分类号： G06F13/38

CPC分类号： G11C7/1006 ,  G11C2207/107 ,  H03M9/00

摘要： In a semiconductor memory system, the memory chips are linked to a memory module in a shared loop forward architecture and connected in a point-to-point connection to a memory controller. Each memory chip includes a high-speed interface circuit including: a read and write data/command-and-address signal re-driver/transmitter path for re-driving serial read data and write data/command-and-address signals not destined for the semiconductor memory chip; and a main signal path which includes a serial-to-parallel converter and a synchronizer for serial-to-parallel converting and synchronizing with a reference clock signal write data/command-and-address signals destined for the semiconductor memory chip as well as a parallel-to-serial converter for parallel-to-serial converting read data signals read from a memory core of the memory chips, and a switch for inserting the parallel-to-serial converted read data signals into the re-driver/transmitter path. Optionally the high-speed interface circuit additionally includes a transparent re-driver/transmitter path not including any synchronizing circuitry.

摘要翻译： 在半导体存储器系统中，存储器芯片被链接到共享回路前向架构中的存储器模块，并且以点对点连接连接到存储器控制器。 每个存储器芯片包括一个高速接口电路，包括：用于重新驱动串行读取数据的读取和写入数据/命令和地址信号重新驱动器/发送器路径，并且写入不预定的数据/命令和地址信号 半导体存储芯片; 以及主信号路径，其包括串行到并行转换器和用于串行到并行转换并与参考时钟信号同步的同步器，写入用于半导体存储器芯片的数据/命令和地址信号以及一个 并行到串行转换器，用于并行到串行转换从存储器芯片的存储器核心读取的读取数据信号，以及用于将并行到串行转换的读取数据信号插入重新驱动器/发送器路径的开关。 可选地，高速接口电路还包括不包括任何同步电路的透明重新驱动器/发射器路径。

公开(公告)号：US20070006010A1

公开(公告)日：2007-01-04

申请号：US11170887

申请日：2005-06-30

申请人： Paul Wallner ,  Peter Gregorius

发明人： Paul Wallner ,  Peter Gregorius

IPC分类号： G06F1/06

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

摘要： A synchronous signal generator is provided that contains a first and second counting and delay circuit, which both are in a subhierarchical position with respect to a reset signal synchronization/delay circuit. The reset signal synchronization/delay circuit and the first and second counting and delay circuit are triggered by a basic clock signal or a first clock signal derived therefrom to be identical in frequency and phase, and contain counting means whose initial and final counting state are adjustable in order to set, in a clocked fashion, the temporal positions of a first and second load signal that are output by the first counting and delay circuit as well as of a FIFO read clock signal that is output by the second counting and delay circuit and thus adapt them to the temporal requirements of a semiconductor memory system containing the synchronous signal generator.

摘要翻译： 提供了同步信号发生器，其包含第一和第二计数和延迟电路，它们都相对于复位信号同步/延迟电路处于分层位置。 复位信号同步/延迟电路和第一和第二计数和延迟电路由基本时钟信号或从其导出的第一时钟信号在频率和相位上相同，并且包含计数装置，其初始和最终计数状态是可调节的 为了以时钟方式设置由第一计数和延迟电路输出的第一和第二负载信号的时间位置以及由第二计数和延迟电路输出的FIFO读取时钟信号，以及 从而使它们适应包含同步信号发生器的半导体存储器系统的时间要求。

公开(公告)号：US07633814B2

公开(公告)日：2009-12-15

申请号：US11735928

申请日：2007-04-16

申请人： Paul Wallner ,  Stefan Dietrich ,  Peter Gregorius

发明人： Paul Wallner ,  Stefan Dietrich ,  Peter Gregorius

IPC分类号： G11C16/04

CPC分类号： G11C7/1051 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： A memory device comprising a memory cell array; an input circuit for receiving command data and providing drive signals to the memory cell array; an output buffer for buffering data read out from the memory cell array; and a timer for driving the output buffer such that the buffered data are provided at an output after a predetermined time interval has elapsed, the predetermined time interval beginning with the provision of the drive signals.

摘要翻译： 一种存储器件，包括存储单元阵列; 用于接收命令数据并向存储单元阵列提供驱动信号的输入电路; 用于缓冲从存储单元阵列读出的数据的输出缓冲器; 以及用于驱动输出缓冲器的定时器，使得在经过预定时间间隔之后的输出处提供缓冲数据，从提供驱动信号开始的预定时间间隔。