公开(公告)号：US07936246B2

公开(公告)日：2011-05-03

申请号：US11973536

申请日：2007-10-09

Applicant: Peter J. Hopper ,  Peter Smeys ,  Andrei Papou

Inventor： Peter J. Hopper ,  Peter Smeys ,  Andrei Papou

IPC: H01F27/24

CPC classification number: H01F17/0013 ,  H01F3/14 ,  H01F27/34 ,  H01F41/046 ,  H01F2017/0066 ,  Y10T29/49078

Abstract: Saturation of nonlinear ferromagnetic core material for on-chip inductors for high current applications is significantly reduced by providing a core design wherein magnetic flux does not form a closed loop, but rather splits into multiple sub-fluxes that are directed to cancel each other. The design enables high on-chip inductance for high current power applications.

Abstract translation: 用于大电流应用的片上电感器的非线性铁磁芯材料的饱和度通过提供其中磁通量不形成闭环但是分成多个子通量的核心设计而显着降低，这些子通量被引导以相互抵消。 该设计可实现高电流功率应用的高片内电感。

公开(公告)号：US07897472B2

公开(公告)日：2011-03-01

申请号：US12624259

申请日：2009-11-23

Applicant: Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Andrei Papou

Inventor： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Andrei Papou

IPC: H01L21/20

CPC classification number: H01L23/645 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/19015 ,  H01L2924/19104 ,  H01L2924/00

Abstract: Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Electroplating is used to form inductor windings in the recess regions. Optionally, a magnetic paste can be applied over the inductor coils.

Abstract translation: 描述了在半导体晶片上形成多个电感器的方法。 将镀层和光致抗蚀剂层施加在半导体晶片上。 使用光刻技术在光致抗蚀剂层中蚀刻凹陷区域，其暴露下面的镀层的部分。 将金属电镀到光致抗蚀剂层的凹陷区域中以形成多个磁芯电感器构件。 介质绝缘层施加在磁芯电感器部件上。 在电介质绝缘层上施加附加的电镀和光致抗蚀剂层。 在新施加的光致抗蚀剂层中形成凹陷区域。 电镀用于在凹陷区域形成电感线圈。 可选地，可以在电感线圈上施加磁性糊。

公开(公告)号：US07872840B1

公开(公告)日：2011-01-18

申请号：US11893847

申请日：2007-08-17

Applicant: Vladislay Vashchenko ,  Peter J. Hopper

Inventor： Vladislay Vashchenko ,  Peter J. Hopper

IPC: H02H9/00

CPC classification number: G11C16/30 ,  H01L27/0259

Abstract: In an ESD protection circuit for an EEPROM erase pin a snapback device is provided for discharging high ESD currents, whereas the snapback device is operated in active mode during low voltage electrical overstress and to discharge post ESD event current by connecting an RC circuit over the control electrode of the snapback device. In order to handle high voltage normal operating conditions the snapback device is deactivated once VDD is applied by pulling the control electrode to ground using a VDD controlled switch.

Abstract translation: 在EEPROM擦除引脚的ESD保护电路中，提供了一个用于放电高ESD电流的快速恢复器件，而在低电压电应力过程中，快速恢复器件工作在主动模式，并通过连接控制器上的RC电路来放电ESD事件电流 回弹装置的电极。 为了处理高电压正常工作状态，通过使用VDD控制开关将控制电极拉到地，一旦施加了VDD，则恢复器件被禁用。

公开(公告)号：US20110007574A1

公开(公告)日：2011-01-13

申请号：US12884519

申请日：2010-09-17

Applicant: Yuri Mirgorodski ,  Peter J. Hopper ,  Roozbeh Parsa

Inventor： Yuri Mirgorodski ,  Peter J. Hopper ,  Roozbeh Parsa

IPC: G11C16/04

CPC classification number: G11C16/10 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and rain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and separated therefrom by intervening dielectric material, the erasing method comprising: biasing the deep N-type well at a selected erase voltage; holding the source and drain regions of the PMOS transistor at the erase voltage or floating; and holding the control gate at ground for a preselected erase time.

Abstract translation: 一种擦除形成在N型半导体材料的深阱中的NVM单元结构的方法，其中NVM单元结构包括形成在N型阱中的PMOS晶体管，PMOS晶体管包括间隔开的p型源极和漏极 在它们之间限定n型沟道区的区域，形成在与N型阱相邻的P型阱中的NMOS晶体管，NMOS晶体管包括间隔开的n型源和限定p型沟道的雨区 导电浮置栅极，其包括在PMOS晶体管的n型沟道区域上延伸并且通过中间介电材料分离的第一部分和在p型沟道区域上延伸并与其分离的第二部分的第一部分 通过插入介电材料和导电控制栅极形成在浮动栅极的第二部分的至少一部分上，并通过介电材料与其隔开， 包括：在所选择的擦除电压下偏置所述深N型阱; 将PMOS晶体管的源极和漏极区域保持在擦除电压或浮置; 并将控制门保持在地面以进行预先选择的擦除时间。

公开(公告)号：US07795047B1

公开(公告)日：2010-09-14

申请号：US11016010

申请日：2004-12-17

Applicant: Vladislav Vashchenko ,  Peter J. Hopper

Inventor： Vladislav Vashchenko ,  Peter J. Hopper

IPC: H01L31/072

CPC classification number: H01L29/7322 ,  H01L27/0259 ,  H01L29/0813

Abstract: In a method and structure for current balancing the emitter current in a multi-finger n-emitter of a BJT or BSCR, back-end or polysilicon resistors are applied between the emitter fingers and the power rail, with the resistors chosen to be larger the closer the emitter fingers are to the collector.

Abstract translation: 在用于电流平衡BJT或BSCR的多指n发射极中的发射极电流的方法和结构中，后端或多晶硅电阻器被施加在发射极和电源轨之间，其中电阻器选择为大于 发射器手指靠近收集器。

公开(公告)号：US20100142239A1

公开(公告)日：2010-06-10

申请号：US12315932

申请日：2008-12-08

Applicant: Peter J. Hopper

Inventor： Peter J. Hopper

IPC: H02M7/537

CPC classification number: H02M7/501

Abstract: In a grid-tie inverter, the DC input is phase and pulse-width modulated to define multiple phase shifted voltage pulses with the width of each pulse being modulated according to the grid AC amplitude for the corresponding portion of the AC phase.

Abstract translation: 在并联逆变器中，直流输入是相位和脉冲宽度调制的，以定义多个相移电压脉冲，每个脉冲的宽度根据AC相位的相应部分的电网AC振幅进行调制。

公开(公告)号：US07718480B1

公开(公告)日：2010-05-18

申请号：US11138221

申请日：2005-05-26

Applicant: Vladislav Vashchenko ,  Marcel ter Book ,  Peter J. Hopper

Inventor： Vladislav Vashchenko ,  Marcel ter Book ,  Peter J. Hopper

IPC: H01L21/00

CPC classification number: H01L27/0266 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/78

Abstract: In an NMOS active clamp device and an NMOS active clamp array with multiple source and drain contacts, the robustness against ESD events is increased by reducing channel resistance through the inclusion of one or more p+ regions formed at least partially in the source and electrically connected to the one or more source contacts.

Abstract translation: 在具有多个源极和漏极触点的NMOS有源钳位装置和NMOS有源钳位阵列中，通过包括至少部分地形成在源极中的一个或多个p +区域并且电连接到 一个或多个源接触。

公开(公告)号：US07642116B1

公开(公告)日：2010-01-05

申请号：US11476525

申请日：2006-06-28

Applicant: Peter J. Hopper ,  Michael Mian ,  Robert Drury

Inventor： Peter J. Hopper ,  Michael Mian ,  Robert Drury

IPC: H01L31/113

CPC classification number: H01L31/1868 ,  H01L31/02162 ,  H01L31/0352 ,  H01L31/103 ,  Y02E10/50

Abstract: The loss of photogenerated electrons to surface electron-hole recombination sites is minimized by utilizing a first p-type surface region to form a depletion region that functions as a first barrier that repels photogenerated electrons from the surface recombination sites, and a second p-type surface region that provides a substantial change in the dopant concentration.

Abstract translation: 通过利用第一p型表面区域形成作为从表面复合位点排斥光生电子的第一屏障的耗尽区域，使光生电子向表面电子 - 空穴复合位点的损失最小化，第二p型 表面区域，其提供掺杂剂浓度的显着变化。

公开(公告)号：US07639464B1

公开(公告)日：2009-12-29

申请号：US11376492

申请日：2006-03-15

Applicant: Vladislav Vashchenko ,  Peter J. Hopper

Inventor： Vladislav Vashchenko ,  Peter J. Hopper

IPC: H02H9/00 ,  H02H3/20

CPC classification number: H01L27/0266

Abstract: In a dual direction ESD protection structure, first and second NMOS devices are serially connected back-to-back by connecting their drains or their sources using a common floating interconnect, while ensuring that the devices remain isolated from each other.

Abstract translation: 在双向ESD保护结构中，第一和第二NMOS器件通过使用公共浮动互连连接它们的漏极或其源极而被背对背地串联连接，同时确保器件保持彼此隔离。

公开(公告)号：US07635614B1

公开(公告)日：2009-12-22

申请号：US11724622

申请日：2007-03-15

Applicant: Vladimir Kuznetsov ,  Vladislav Vashchenko ,  Peter J. Hopper

Inventor： Vladimir Kuznetsov ,  Vladislav Vashchenko ,  Peter J. Hopper

IPC: H01L21/323 ,  H01L29/74

CPC classification number: H01L29/7436 ,  H01L29/7404 ,  H01L29/749

Abstract: An NLDMOS SCR device based on an LDMOS fabrication process includes a dual gate to provide controllable switching characteristics to allow it to be used for ESD protection of fast switching voltage regulators.

Abstract translation: 基于LDMOS制造工艺的NLDMOS SCR器件包括提供可控开关特性以允许其用于快速开关电压调节器的ESD保护的双栅极。