公开(公告)号：US07536514B2

公开(公告)日：2009-05-19

申请号：US11225655

申请日：2005-09-13

申请人： Wayne Melvin Barrett ,  Kenneth Michael Valk ,  Brian T. Vanderpool

发明人： Wayne Melvin Barrett ,  Kenneth Michael Valk ,  Brian T. Vanderpool

IPC分类号： G06F12/06

CPC分类号： G06F13/1663 ,  G06F12/0817

摘要： An early return indication is used to notify a first communications interface, prior to a response being received from any of a plurality of sources coupled to a second communications interface, that the return data can be used by the first communications interface when it is received thereby from a source of the return data if the source has an exclusive copy of the return data. By doing so, the first communications interface can often prepare for forwarding the return data over its associated communication link such that the data can be forwarded with little or no latency once the data is retrieved from its source, and may be able to initiate the return of data over the communication link prior to all responses being received from the other sources. The early return indication may also serves as an early coherency indication in that the first communications interface is no longer required to wait for updating of a coherency directory to complete prior to forwarding the return data over the communication link.

摘要翻译： 早期返回指示用于在从与第二通信接口耦合的多个源中的任一个接收到响应之前通知第一通信接口，使得第一通信接口在接收时可以由第一通信接口使用返回数据 来自返回数据的源，如果源具有返回数据的排他副本。 通过这样做，第一通信接口通常可以准备通过其相关联的通信链路转发返回数据，使得一旦数据从源中检索出来，数据可以很少或没有等待时间转发，并且可能能够启动返回 在从其他来源接收到所有响应之前通过通信链路的数据。 早期返回指示还可以用作早期一致性指示，因为在通过通信链路转发返回数据之前，第一通信接口不再需要等待更新相干性目录来完成。

公开(公告)号：US06754753B2

公开(公告)日：2004-06-22

申请号：US09844584

申请日：2001-04-27

申请人： Bruce Leroy Beukema ,  Richard Charles Booth ,  David Robert Engebretsen ,  Thomas Rembert Sand ,  Kenneth Michael Valk

发明人： Bruce Leroy Beukema ,  Richard Charles Booth ,  David Robert Engebretsen ,  Thomas Rembert Sand ,  Kenneth Michael Valk

IPC分类号： G06F1516

CPC分类号： G06F9/52

摘要： A clustered computer system, bridge device and method include support for an atomic ownership change operation that ensures orderly and reliable ownership management of an input/output (I/O) bridge device. A lock indicator is associated with a bridge device, and is used to indicate a “locked” or “unlocked” status of the bridge device. Whenever the lock indicator indicates that the bridge device is unlocked, an atomic operation such as a read request to a lock indicator register is utilized to both set the indicator to indicate a locked status for the bridge device, and to associate the bridge device with a source node that initiated the atomic operation. In connection with the lock indicator, write access to one or more configuration parameter registers is controlled such that only the node that is associated with the bridge device is permitted to update such configuration parameter registers.

摘要翻译： 集群计算机系统，桥接器件和方法包括支持原子所有权更改操作，确保输入/输出（I / O）桥接器件的有序可靠的所有权管理。 锁定指示器与桥接设备相关联，并用于指示桥接设备的“锁定”或“解锁”状态。 每当锁定指示器指示桥接设备被解锁时，利用诸如对锁定指示器寄存器的读取请求的原子操作来将指示器设置为指示桥接设备的锁定状态，并且将桥接设备与 源节点启动原子操作。 与锁定指示器相关联，控制对一个或多个配置参数寄存器的写入访问，使得仅允许与桥接设备相关联的节点更新这样的配置参数寄存器。

公开(公告)号：US06643818B1

公开(公告)日：2003-11-04

申请号：US09443521

申请日：1999-11-19

申请人： Kenneth Michael Valk

发明人： Kenneth Michael Valk

IPC分类号： H04L100

CPC分类号： H04L1/0063

摘要： A method and apparatus is disclosed which enhances the integrity of transmitted data or detects when random data is being received which might indicate that a receiver or a transmitter is open or that random data is otherwise being transmitted. A stream of data transmitted in packets having an error code associated with each packet is received into a receiver. The receiver has an error code checker to check the error code of each packet to determine if the data packet has been transmitted error-free. The results of the error checks for n sequential packets are stored in a shift register or counter. An incoming packet then undergoes an error code check and the results of the previous n sequential packets are considered. If a predetermined number of the previous n sequential packets has a transmission error n, then the method decides to reject or accept the error packet based on the quality of data integrity. When a 32-bit CRC error code is used, an 8-bit shift register is sufficient to prevent the acceptance of a packet of random data that may otherwise be accepted.

摘要翻译： 公开了一种增强传输数据的完整性或检测何时正在接收可能指示接收机或发射机打开或者随机数据被另外传输的随机数据的方法和装置。 在具有与每个分组相关联的错误代码的分组中传输的数据流被接收到接收机中。 接收机有一个错误代码检查器，用于检查每个数据包的错误代码，以确定数据包是否已经无误传输。 n个顺序包的错误检查结果存储在移位寄存器或计数器中。 然后，传入的数据包经历错误代码检查，并考虑先前的n个顺序数据包的结果。 如果预定数量的先前n个顺序分组具有传输错误n，则该方法基于数​​据完整性的质量决定拒绝或接受错误分组。 当使用32位CRC错误代码时，8位移位寄存器足以防止接受可能被接受的随机数据包。

公开(公告)号：US20090019228A1

公开(公告)日：2009-01-15

申请号：US11776731

申请日：2007-07-12

申请人： Jeffrey Douglas Brown ,  Russell Dean Hoover ,  Eric Oliver Mejdrich ,  Kenneth Michael Valk

发明人： Jeffrey Douglas Brown ,  Russell Dean Hoover ,  Eric Oliver Mejdrich ,  Kenneth Michael Valk

IPC分类号： G06F12/12

CPC分类号： G06F12/0895 ,  Y02D10/13

摘要： According to embodiments of the invention, a step value and a step-interval cache coherency protocol may be used to update and invalidate data stored within cache memory. A step value may be an integer value and may be stored within a cache directory entry associated with data in the memory cache. Upon reception of a cache read request, along with the normal address comparison to determine if the data is located within the cache a current step value may be compared with the stored step value to determine if the data is current. If the step values match, the data may be current and a cache hit may occur. However, if the step values do not match, the requested data may be provided from another source. Furthermore, an application may update the current step value to invalidate old data stored within the cache and associated with a different step value.

摘要翻译： 根据本发明的实施例，可以使用步长值和步进间隔高速缓存一致性协议来更新和使存储在高速缓冲存储器中的数据无效。 步数值可以是整数值，并且可以存储在与存储器高速缓存中的数据相关联的高速缓存目录条目中。 在接收到缓存读取请求时，连同正常地址比较以确定数据是否位于高速缓存内，可以将当前步长值与存储的步长值进行比较，以确定数据是否为当前值。 如果步数值匹配，数据可能是当前的，并且可能会发生高速缓存命中。 然而，如果步骤值不匹配，则可以从另一个源提供所请求的数据。 此外，应用程序可以更新当前步骤值以使存储在高速缓存中并与不同步长值相关联的旧数据无效。

公开(公告)号：US06275876B1

公开(公告)日：2001-08-14

申请号：US09316243

申请日：1999-05-21

申请人： Kenneth Michael Valk ,  Thomas Rembert Sand ,  Ronald Edward Fuhs ,  Gregory Michael Nordstrom ,  Bruce Leroy Beukema

发明人： Kenneth Michael Valk ,  Thomas Rembert Sand ,  Ronald Edward Fuhs ,  Gregory Michael Nordstrom ,  Bruce Leroy Beukema

IPC分类号： G06F1312

CPC分类号： G06F13/126

摘要： A computing system includes a processing system, at least a first register, and a control system. The processing system generates a first instruction set and a first address for storing a first completion status for the first instruction set. The first register receives the first address from the processing system. The control system communicates the first instruction set received from the processing system to an external device. The control system receives the first completion status from the external device, accesses the first register to determine the first address for the first instruction set, and stores the first completion status in the determined first address.

摘要翻译： 计算系统包括处理系统，至少第一寄存器和控制系统。 处理系统产生第一指令集和第一地址，用于存储第一指令集的第一完成状态。 第一个寄存器从处理系统接收第一个地址。 控制系统将从处理系统接收的第一指令集传送到外部设备。 控制系统从外部设备接收第一完成状态，访问第一寄存器以确定第一指令集的第一地址，并将第一完成状态存储在所确定的第一地址中。

公开(公告)号：US5787094A

公开(公告)日：1998-07-28

申请号：US656950

申请日：1996-06-06

申请人： Delbert Raymond Cecchi ,  Marius V. Dina ,  Curtis Walter Preuss ,  Kenneth Michael Valk

发明人： Delbert Raymond Cecchi ,  Marius V. Dina ,  Curtis Walter Preuss ,  Kenneth Michael Valk

IPC分类号： G06F11/263 ,  G06F11/267 ,  G06F11/10 ,  H03M13/00

CPC分类号： G06F11/221 ,  G01R31/318385 ,  G06F11/263

摘要： A method and apparatus that can test self-timed parallel interfaces operating at system speed. An output stage is provided for queuing a test packet and providing the test packet to an input stage. The packet contains a data bit stream and error detection code such as cyclic redundancy check code. The input stage is coupled to the output stage and receives the test packet to determine the correctness of the data bit stream. On the input stage, the error detection code verifier recalculates the error detection code and compares the recalculated error detection code with the error detection code attached to the data bit stream to determine the correctness of the data bit steam. The output queue has a first input port for receiving data from drivers on the interface and a second input port for receiving a pseudo random data bit stream. A pseudo random data generator generates a pseudo random data bit stream. The data bit stream may be packetized according to a predetermined protocol. An off-chip signal of the output stage may be provided to the inputs of the input stage to produce an on-chip copy of off-chip data.

摘要翻译： 可以测试以系统速度运行的自定时并行接口的方法和装置。 提供输出级用于排队测试分组并将测试分组提供给输入级。 分组包含数据比特流和诸如循环冗余校验码的错误检测码。 输入级耦合到输出级并接收测试数据包以确定数据位流的正确性。 在输入级上，错误检测码验证器重新计算错误检测码，并将重新计算的错误检测码与附加到数据比特流的错误检测码进行比较，以确定数据比特流的正确性。 输出队列具有用于从接口上的驱动器接收数据的第一输入端口和用于接收伪随机数据位流的第二输入端口。 伪随机数据生成器生成伪随机数据比特流。 可以根据预定协议对数据比特流进行分组化。 可以将输出级的片外信号提供给输入级的输入，以产生片外数据的片上拷贝。

公开(公告)号：US07197536B2

公开(公告)日：2007-03-27

申请号：US09845933

申请日：2001-04-30

申请人： Bruce Leroy Beukema ,  Richard Charles Booth ,  David Robert Engebretsen ,  Thomas Rembert Sand ,  Kenneth Michael Valk

发明人： Bruce Leroy Beukema ,  Richard Charles Booth ,  David Robert Engebretsen ,  Thomas Rembert Sand ,  Kenneth Michael Valk

IPC分类号： G06F15/16 ,  H04Q11/00

CPC分类号： H04L29/06 ,  H04L29/12254 ,  H04L61/2038

摘要： A circuit arrangement, node, clustered computer system, and method incorporate a primitive communication mechanism for use in exchanging data between adjacent nodes coupled via a point-to-point network. A plurality of network ports are used to couple a node to other nodes in the clustered computer system over point-to-point network interconnects, and a plurality of communication registers are associated with each of the network ports for the purpose of storing data received through their associated network ports. A node desiring to communicate information to another node receives a port identifier from the other node that identifies the network port on the other node through which the pair of nodes are coupled. The port identifier is then used by the node to communicate data to the other node through the use of one or more write operations directed to the communication register on the other node that is associated with the network port identified by the port identifier. On the other node, a control circuit is used to automatically notify the other node whenever data is stored in any of its communication registers, e.g., by generating an interrupt in response to non-zero data being stored in any of such communication registers.

摘要翻译： 电路布置，节点，集群计算机系统和方法包含用于在经由点对点网络耦合的相邻节点之间交换数据的原始通信机制。 多个网络端口用于通过点对点网络互连将节点耦合到群集计算机系统中的其他节点，并且多个通信寄存器与每个网络端口相关联，用于存储通过 其关联的网络端口。 希望向另一节点传送信息的节点从另一个节点接收一个端口标识符，该端口标识通过该对节点耦合的另一个节点上的网络端口。 然后端口标识符被节点用于通过使用针对与由端口标识符标识的网络端口相关联的另一节点上的通信寄存器的一个或多个写入操作来向另一个节点传送数据。 在另一节点上，当数据存储在其任何通信寄存器中时，例如通过响应于非零数据被存储在任何这样的通信寄存器中而产生中断，控制电路被用于自动通知另一个节点。

公开(公告)号：US07110402B2

公开(公告)日：2006-09-19

申请号：US10933599

申请日：2004-09-03

申请人： Timothy Roy Block ,  Richard Charles Booth ,  David Robert Engebretsen ,  Thomas Rembert Sand ,  Kenneth Michael Valk

发明人： Timothy Roy Block ,  Richard Charles Booth ,  David Robert Engebretsen ,  Thomas Rembert Sand ,  Kenneth Michael Valk

IPC分类号： H04L12/28

CPC分类号： H04L49/351 ,  H04L49/3009

摘要： A method and system for communication in a system area network (SAN) data processing system are described. The SAN includes a plurality of interconnected nodes that each have at least one port for communication. To avoid communication-induced errors that may arise, for example, if multiple nodes share the same node ID, the port of a node in the SAN is marked as “fenced” to prevent transmission of packets of a first traffic type while permitting transmission of packets of a second traffic type. The marking of the port may be recorded, for example, in a configuration register of the port. While the port is fenced, only packets of other than the first traffic type are routed via the port. In one preferred embodiment, the second traffic type represents SAN configuration traffic, and the first traffic type represents non-configuration traffic. In this preferred embodiment, the marking of the port may be removed following communication of configuration traffic utilized to negotiate unique node ID throughout the SAN.

公开(公告)号：US06006255A

公开(公告)日：1999-12-21

申请号：US628598

申请日：1996-04-05

申请人： Russell Dean Hoover ,  George Wayne Nation ,  Kenneth Michael Valk

发明人： Russell Dean Hoover ,  George Wayne Nation ,  Kenneth Michael Valk

IPC分类号： H04L29/06 ,  H04L29/08 ,  G06F13/00

CPC分类号： H04L29/06 ,  H04L69/32

摘要： A networked computer system and method of communicating classify request packets into multiple classes, with one class devoted to non-propagable requests that may be handled locally by destination nodes in the computer system. The multiple classes of requests are separately handled in the networked computer system such that an inability of a node to handle a request in another class does not hinder the ability of the node to process non-propagable requests, thereby avoiding deadlocks in the computer system.

摘要翻译： 一种联网的计算机系统和通信方法，将请求分组分类为多个类，其中一类专门用于计算机系统中目的地节点本地处理的不可传播请求。 在联网的计算机系统中分开处理多个请求类别，使得节点不能处理另一类中的请求不妨碍节点处理不可传播请求的能力，从而避免计算机系统中的死锁。

公开(公告)号：US08804960B2

公开(公告)日：2014-08-12

申请号：US12709662

申请日：2010-02-22

申请人： Wayne Melvin Barrett ,  Kenneth Michael Valk

发明人： Wayne Melvin Barrett ,  Kenneth Michael Valk

IPC分类号： H04L9/12 ,  H04L29/06 ,  G06F13/00

CPC分类号： H04L63/0457 ,  G06F1/12 ,  G06F13/00 ,  H04L2209/12

摘要： A method and circuit for implementing known scrambling relationship among multiple serial links, and a design structure on which the subject circuit resides are provided. A transmit Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for scrambling transmitted data. A receive Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for descrambling received data. Each of the transmit LFSRs is initialized to a unique value. Each transmit LFSR conveys a current unique value to a receive LFSR for synchronizing the transmit LFSR and receive LFSR to begin scrambling and descrambling data.

摘要翻译： 一种用于实现多个串行链路之间的已知加扰关系的方法和电路，以及设置有该主题电路所在的设计结构。 发送线性反馈移位寄存器（LFSR）与多个串行链路中的每一个一起提供，用于加扰发送的数据。 每个多个串行链路提供接收线性反馈移位寄存器（LFSR），用于解扰接收到的数据。 每个发送LFSR被初始化为唯一值。 每个发送的LFSR向接收LFSR传送当前唯一的值以使发送LFSR同步并且接收LFSR以开始加扰和解扰数据。