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    Process for manufacturing low-cost and high-quality SOI substrates
    12.
    发明授权
    Process for manufacturing low-cost and high-quality SOI substrates 有权

    公开(公告)号：US07071073B2

    公开(公告)日：2006-07-04

    申请号：US10331189

    申请日：2002-12-26

    申请人： Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

    发明人： Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76262 ,  H01L21/31662 ,  H01L21/76208

    摘要： For manufacturing an SOI substrate, the following steps are carried out: providing a wafer of semiconductor material; forming, inside the wafer, a plurality of passages forming a labyrinthine cavity and laterally delimiting a plurality of pillars of semiconductor material; and oxidizing the pillars of semiconductor material to form a buried insulating layer. For forming the labyrinthine cavity, a trench is first formed in a substrate; an epitaxial layer is grown, which closes the trench at the top; the wafer is annealed so as to deform the pillars and cause them to assume a minimum-energy handlebar-like shape, and a peripheral portion of the wafer is removed to reach the labyrinthine cavity, and side inlet openings are formed in the labyrinthine cavity. Oxidation is performed by feeding an oxidizing fluid through the side inlet openings.

    Process for manufacturing a SOI wafer with buried oxide regions without cusps
    13.
    发明授权
    Process for manufacturing a SOI wafer with buried oxide regions without cusps 失效
    用于制造具有埋藏氧化物区域的SOI晶片的方法，而不具有尖端

    公开(公告)号：US06362070B1

    公开(公告)日：2002-03-26

    申请号：US09558934

    申请日：2000-04-26

    申请人： Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

    发明人： Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

    IPC分类号： H01L2176

    CPC分类号： H01L21/02238 ,  H01L21/02299 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/76208 ,  H01L21/76248

    摘要： A process for manufacturing a SOI wafer with buried oxide regions without cusps that includes forming, in a wafer of monocrystalline semiconductor material, trenches extending between, and delimiting laterally, protruding regions; forming masking regions, implanted with nitrogen ions, the masking regions surrounding completely the tips of the protruding regions; and forming retarding regions on the bottom of the trenches, wherein nitrogen is implanted at a lower dose than the masking regions. A thermal oxidation is then carried out and starts at the bottom portion of the protruding regions and then proceeds downwards; thereby, a continuous region of buried oxide is formed and is overlaid by non-oxidized regions corresponding to the tips of the protruding regions and forming nucleus regions for a subsequent epitaxial growth. The masking regions and the retarding regions are formed through two successive implants, including an angle implant, wherein the protruding regions shield the bottom portions of the adjacent protruding regions, as well as the bottom of the trenches, and a vertical implant is made perpendicularly to the wafer.

    摘要翻译： 一种用于制造具有埋藏氧化物区域而没有尖端的SOI晶片的方法，包括在单晶半导体材料的晶片中形成在横向延伸并限定突出区域的沟槽; 形成掩蔽区域，注入氮离子，掩蔽区域完全围绕突出区域的尖端; 以及在沟槽的底部形成延迟区域，其中以比掩蔽区域低的剂量注入氮。 然后进行热氧化，并从突出区域的底部开始，然后向下移动; 由此，形成了埋入氧化物的连续区域，并且由对应于突出区域的尖端的非氧化区域覆盖并形成用于随后的外延生长的核区域。 掩模区域和延迟区域通过两个连续的植入物形成，包括角度注入，其中突出区域屏蔽相邻突出区域的底部以及沟槽的底部，垂直植入物垂直于 晶圆。

    Process for manufacturing a semiconductor wafer having SOI-insulated wells and semiconductor wafer thereby manufactured
    15.
    发明授权
    Process for manufacturing a semiconductor wafer having SOI-insulated wells and semiconductor wafer thereby manufactured 有权
    制造具有SOI绝缘阱和半导体晶片的半导体晶片的制造方法

    公开(公告)号：US07906406B2

    公开(公告)日：2011-03-15

    申请号：US11879738

    申请日：2007-07-17

    申请人： Gabriele Barlocchi ,  Pietro Corona ,  Flavio Francesco Villa

    发明人： Gabriele Barlocchi ,  Pietro Corona ,  Flavio Francesco Villa

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76264 ,  H01L21/7682

    摘要： A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.

    摘要翻译： 制造包括SOI绝缘阱的半导体晶片的工艺包括在半导体主体的管芯区域中形成穿过掩埋腔并分布在管芯区域中的掩埋腔和半导体结构元件。 该方法还包括选择性地将第一相邻的半导体结构元件氧化并设置在封闭区域内的步骤，并且防止第二半导体结构元件在封闭区域外的氧化，从而在闭合区域内选择性地形成管芯埋入介电层。

    PROCESS FOR MANUFACTURING A MEMBRANE OF SEMICONDUCTOR MATERIAL INTEGRATED IN, AND ELECTRICALLY INSULATED FROM, A SUBSTRATE
    16.
    发明申请
    PROCESS FOR MANUFACTURING A MEMBRANE OF SEMICONDUCTOR MATERIAL INTEGRATED IN, AND ELECTRICALLY INSULATED FROM, A SUBSTRATE 有权
    一种制造半导体材料膜的方法，集成在一个基板上并电绝缘

    公开(公告)号：US20080224242A1

    公开(公告)日：2008-09-18

    申请号：US12047830

    申请日：2008-03-13

    申请人： Flavio Franceso Villa ,  Pietro Corona ,  Chantal Combi ,  Lorenzo Baldo ,  Gabriele Barlocchi

    发明人： Flavio Franceso Villa ,  Pietro Corona ,  Chantal Combi ,  Lorenzo Baldo ,  Gabriele Barlocchi

    IPC分类号： H01L29/96 ,  H01L21/02

    CPC分类号： B81C1/00158

    摘要： A process for manufacturing an integrated membrane made of semiconductor material includes the step of forming, in a monolithic body of semiconductor material having a front face, a buried cavity, extending at a distance from the front face and delimiting with the front face a surface region of the monolithic body, the surface region forming a membrane that is suspended above the buried cavity. The process further envisages the step of forming an insulation structure in a surface portion of the monolithic body to electrically insulate the membrane from the monolithic body; and the further and distinct step of setting the insulation structure at a distance from the membrane so that it will be positioned outside the membrane at a non-zero distance of separation.

    摘要翻译： 制造由半导体材料制成的集成膜的方法包括以下步骤：在具有前表面的半导体材料的整体中形成一个与前表面相距一定距离的掩埋腔， 的单体，表面区域形成悬浮在掩埋腔上方的膜。 该方法进一步设想在整体式主体的表面部分形成绝缘结构以将膜与整体式电绝缘的步骤; 以及将绝缘结构设置在离膜一定距离处的进一步和不同的步骤，使得其将以非零分离距离定位在膜的外部。

    Process for manufacturing thick suspended structures of semiconductor material
    18.
    发明申请
    Process for manufacturing thick suspended structures of semiconductor material 有权
    用于制造半导体材料的厚悬浮结构的方法

    公开(公告)号：US20070126071A1

    公开(公告)日：2007-06-07

    申请号：US11541376

    申请日：2006-09-27

    申请人： Pietro Corona ,  Flavio Villa ,  Gabriele Barlocchi

    发明人： Pietro Corona ,  Flavio Villa ,  Gabriele Barlocchi

    IPC分类号： H01L29/84 ,  H01L21/00

    CPC分类号： B81C1/00158 ,  B81B2201/025 ,  B81B2203/0109 ,  B81B2203/0315

    摘要： A process for manufacturing a suspended structure of semiconductor material envisages the steps of: providing a monolithic body of semiconductor material having a front face; forming a buried cavity within the monolithic body, extending at a distance from the front face and delimiting, with the front face, a surface region of the monolithic body, said surface region having a first thickness; carrying out a thickening thermal treatment such as to cause a migration of semiconductor material of the monolithic body towards the surface region and thus form a suspended structure above the buried cavity, the suspended structure having a second thickness greater than the first thickness. The thickening thermal treatment is an annealing treatment.

    摘要翻译： 制造半导体材料的悬浮结构的方法设想的步骤：提供具有正面的半导体材料的整体; 在所述整体式主体内形成掩埋空腔，所述掩埋腔在所述前表面的一定距离处延伸并且与所述前表面一起界定所述整体式主体的表面区域，所述表面区域具有第一厚度; 进行增稠热处理，使得整体式体的半导体材料朝向表面区域移动，从而在掩埋空腔之上形成悬浮结构，该悬浮结构的第二厚度大于第一厚度。 增稠热处理是退火处理。

    Integrated differential pressure sensor and manufacturing process thereof
    19.
    发明申请
    Integrated differential pressure sensor and manufacturing process thereof 有权
    集成差压传感器及其制造工艺

    公开(公告)号：US20060260408A1

    公开(公告)日：2006-11-23

    申请号：US11417683

    申请日：2006-05-04

    申请人： Flavio Villa ,  Pietro Corona ,  Gabriele Barlocchi ,  Lorenzo Baldo

    发明人： Flavio Villa ,  Pietro Corona ,  Gabriele Barlocchi ,  Lorenzo Baldo

    IPC分类号： B05D5/12 ,  G01L7/08

    CPC分类号： G01L9/0045 ,  G01L13/025

    摘要： A process for manufacturing an integrated differential pressure sensor includes forming, in a monolithic body of semiconductor material having a first face and a second face, a cavity extending at a distance from the first face and delimiting therewith a flexible membrane, forming an access passage in fluid communication with the cavity, and forming, in the flexible membrane, at least one transduction element configured so as to convert a deformation of the flexible membrane into electrical signals. The cavity is formed in a position set at a distance from the second face and delimits, together with the second face, a portion of the monolithic body. In order to form the access passage, the monolithic body is etched so as to form an access trench extending through it.

    摘要翻译： 一种用于制造集成差压传感器的方法，包括在具有第一面和第二面的半导体材料的整体中形成一个与第一面相距一定距离的空腔，并将其限定在柔性膜上，形成入口通道 与空腔流体连通，以及在柔性膜中形成至少一个换能元件，其构造成将柔性膜的变形转换为电信号。 空腔形成在距第二面一定距离处的位置，并与第二面一起界定整体式的一部分。 为了形成进入通道，对整体式主体进行蚀刻以便形成延伸通过其的通道沟槽。

    Process for manufacturing a semiconductor wafer having SOI-insulated wells and semiconductor wafer thereby manufactured
    20.
    发明授权
    Process for manufacturing a semiconductor wafer having SOI-insulated wells and semiconductor wafer thereby manufactured 有权
    制造具有SOI绝缘阱和半导体晶片的半导体晶片的制造方法

    公开(公告)号：US09105690B2

    公开(公告)日：2015-08-11

    申请号：US13023039

    申请日：2011-02-08

    申请人： Gabriele Barlocchi ,  Pietro Corona ,  Flavio Francesco Villa

    发明人： Gabriele Barlocchi ,  Pietro Corona ,  Flavio Francesco Villa

    IPC分类号： H01L29/08 ,  H01L21/762 ,  H01L21/768

    CPC分类号： H01L21/76264 ,  H01L21/7682

    摘要： A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.

    摘要翻译： 制造包括SOI绝缘阱的半导体晶片的工艺包括在半导体主体的管芯区域中形成穿过掩埋腔并分布在管芯区域中的掩埋腔和半导体结构元件。 该方法还包括选择性地将第一相邻的半导体结构元件氧化并设置在封闭区域内的步骤，并且防止第二半导体结构元件在封闭区域外的氧化，从而在闭合区域内选择性地形成管芯埋入介电层。