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    Variable Delay
    11.
    发明申请
    Variable Delay 审中-公开

    公开(公告)号：US20190089360A1

    公开(公告)日：2019-03-21

    申请号：US15711924

    申请日：2017-09-21

    Applicant: Qualcomm Incorporated

    Inventor： Masoud Roham

    IPC: H03L7/081 ,  H03L7/18 ,  H03L7/08 ,  H03L7/07 ,  H03L7/089 ,  H03L7/189 ,  H03D3/24 ,  H03K5/135 ,  H03K5/131

    CPC classification number: H03L7/0814 ,  H03D3/241 ,  H03K5/131 ,  H03K5/135 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0818 ,  H03L7/0893 ,  H03L7/0995 ,  H03L7/1806 ,  H03L7/189

    Abstract: This disclosure describes controlling a variable delay system with a control signal generated in a phase-locked loop (PLL). Furthermore, aspects describe generating a compensation current based on a number of edges of pulses propagating through a variable delay line including multiple delay elements. The number of edges propagating through the variable delay is determined by computing a difference between a number of edges entering the variable delay line and a number of edges exiting the variable delay line. The compensation current is derived from a mirrored version of the current of the control signal of the PLL. Thus, the techniques and systems in this disclosure provide accurate and repeatable control of a variable delay line over variations in temperature and process using low-power circuits. Furthermore, the input signal to the variable delay line may be asynchronous with respect to a system clock or a reference signal of the PLL.

    Receivers for high density and low latency chip-to-chip links
    14.
    发明授权
    Receivers for high density and low latency chip-to-chip links 有权

    公开(公告)号：US12028057B2

    公开(公告)日：2024-07-02

    申请号：US17951790

    申请日：2022-09-23

    Applicant: QUALCOMM Incorporated

    Inventor： Masoud Roham

    IPC: H03K17/56 ,  H03H7/06 ,  H03K19/20

    CPC classification number: H03K17/56 ,  H03H7/06 ,  H03K19/20

    Abstract: A system includes a receiver. The receiver includes an input stage having an input and an output, and a first resistor coupled between the output of the input stage and the input of the input stage. The receiver also includes an output stage having an input and an output, wherein the input of the output stage is coupled to the output of the input stage, and a feedback path coupled between the output of the output stage and the input of the input stage, the feedback path including a second resistor.

    CHIP SEAL RING FOR CAPACITIVE TOUCH SENSING
    17.
    发明申请
    CHIP SEAL RING FOR CAPACITIVE TOUCH SENSING 审中-公开

    公开(公告)号：US20180307342A1

    公开(公告)日：2018-10-25

    申请号：US15491877

    申请日：2017-04-19

    Applicant: QUALCOMM Incorporated

    Inventor： Masoud Roham ,  Mishel Matloubian

    IPC: G06F3/044 ,  G06K9/00

    CPC classification number: G06F3/044 ,  G06K9/0002

    Abstract: This disclosure provides systems, methods and apparatus for capacitive touch sensing. In one aspect, a chip seal ring having an integrated capacitive sense plate is provided. In some implementations, a capacitance of the integrated sense plate to a finger may be used to detect the presence of the finger. In some implementations, a fringe capacitance of the seal ring sense plate to the finger is used to detect the presence of the finger. The chip may be sensor chip, for example, a fingerprint sensor chip, and may be implemented in an electronic device.

    LEVEL SHIFTER APPLICABLE TO LOW VOLTAGE DOMAIN TO HIGH VOLTAGE DOMAIN CONVERSION
    18.
    发明申请
    LEVEL SHIFTER APPLICABLE TO LOW VOLTAGE DOMAIN TO HIGH VOLTAGE DOMAIN CONVERSION 有权

    公开(公告)号：US20170085265A1

    公开(公告)日：2017-03-23

    申请号：US14859030

    申请日：2015-09-18

    Applicant: QUALCOMM Incorporated

    Inventor： Masoud Roham ,  Yanjie Meng

    IPC: H03K19/0185

    CPC classification number: H03K19/018521 ,  H03K3/35613 ,  H03K3/356182

    Abstract: A level shifter includes a latch circuit having a first FET and a second FET; an input circuit having a third FET and a fourth FET, the gates of the first and second FETs being coupled to the drains of the fourth and third FETs, respectively; a first resistive device (resistor, diode-connected FET) coupled between and in series with the first and third FETs between a first voltage rail and a second voltage rail; and a second resistive device (resistor, diode-connected FET) coupled between and in series with the second and fourth FETs between the first and second voltage rails. The gates of the third and fourth FETs are configured to receive a first set of complementary voltages, and a second set of complementary voltages are configured to be generated at the gates of the first and second FETs, respectively. The second set of complementary voltages are based on the first set of complementary voltages.

    CALIBRATED TEMPERATURE SENSING SYSTEM
    19.
    发明申请
    CALIBRATED TEMPERATURE SENSING SYSTEM 审中-公开
    校准温度传感系统

    公开(公告)号：US20160252409A1

    公开(公告)日：2016-09-01

    申请号：US14634371

    申请日：2015-02-27

    Applicant: QUALCOMM, Incorporated

    Inventor： Li Lu ,  Masoud Roham ,  Liang Dai ,  Anand Meruva

    IPC: G01K19/00 ,  G01K7/22

    CPC classification number: G01K19/00 ,  G01K7/01 ,  G01K7/22 ,  G01K15/005 ,  G05F3/225

    Abstract: Systems and methods for sensing temperature on a chip are described herein. In one aspect, a temperature sensing system includes a sensing circuit with matching diode devices for providing corresponding diode voltages proportional to currents through the diode devices. The system also includes a digital code calculation unit for generating a plurality of digital code values based on first and second reference voltages and the diode voltages and a digital calibration engine configured for computing a calibrated temperature based on the plurality of digital codes. The system further includes a switching circuit for routing the diode voltages, during first and second times, to diode voltage input terminals of the digital code calculation unit.

    Abstract translation: 本文描述了用于感测芯片上的温度的系统和方法。 在一个方面，温度感测系统包括具有匹配二极管器件的感测电路，用于提供与通过二极管器件的电流成比例的相应的二极管电压。 该系统还包括一个数字代码计算单元，用于基于第一和第二参考电压和二极管电压产生多个数字代码值，以及数字校准引擎，被配置为基于多个数字代码来计算校准温度。 该系统还包括用于在第一次和第二次期间将二极管电压布置到数字代码计算单元的二极管电压输入端的开关电路。

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