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公开(公告)号：US09312848B2
公开(公告)日：2016-04-12
申请号：US14511800
申请日：2014-10-10
Applicant: QUALCOMM Incorporated
Inventor： Xinwang Zhang , Vijayakumar Dhanasekaran , Le Wang , Ankit Srivastava
CPC classification number: H03K17/161 , H03F1/26 , H03F2200/372 , H03K17/167 , H03K2217/0072
Abstract: A driver circuit includes detectors responsive to the operating region that a driven switch is operating in. The driver circuit is operative to drive the gate of the driven switch at a speed responsive to the output of the detectors.
Abstract translation: 驱动器电路包括响应于操作区域的检测器，驱动开关正在操作。驱动器电路用于以响应于检测器的输出的速度驱动从动开关的门。
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12.发明授权公开(公告)号：US09182767B2
公开(公告)日：2015-11-10
申请号：US13794268
申请日：2013-03-11
Applicant: QUALCOMM Incorporated
Inventor： Ankit Srivastava , Matthew David Sienko , Eugene Robert Worley
CPC classification number: G05F1/10 , H01L27/0274 , H01L27/0277 , H01L27/0629 , H02H3/006 , H02H9/041 , H02H9/046
Abstract: A device includes a snapback clamp circuit configured to clamp a supply voltage in response to the supply voltage exceeding a trigger voltage level. In at least one embodiment, the snapback clamp circuit includes a clamp transistor and a programmable resistance portion that is responsive to a control signal to calibrate the trigger voltage level. Alternatively or in addition, the snapback clamp circuit may include a programmable bias device configured to calibrate the trigger voltage level by biasing a gate terminal of the clamp transistor. In another particular embodiment, a method of calibrating a snapback clamp circuit is disclosed. In another particular embodiment, a method of operating an integrated circuit is disclosed.
Abstract translation: 一种设备包括一个快速恢复钳位电路，配置成响应于超过触发电压电平的电源电压来钳位电源电压。 在至少一个实施例中，快速恢复钳位电路包括钳位晶体管和可编程电阻部分，其响应于控制信号来校准触发电压电平。 或者或另外，快速恢复钳位电路可以包括可编程偏置装置，其被配置为通过偏置钳位晶体管的栅极端子来校准触发电压电平。 在另一个具体实施例中，公开了一种校准快速恢复钳位电路的方法。 在另一个具体实施例中，公开了一种操作集成电路的方法。
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公开(公告)号：US20140204488A1
公开(公告)日：2014-07-24
申请号：US13745949
申请日：2013-01-21
Applicant: QUALCOMM INCORPORATED
Inventor： Eugene R. Worley , Mingliang Wang , Ankit Srivastava , Song S. Shi
CPC classification number: H02H9/046
Abstract: In a particular embodiment, an apparatus includes an electrostatic discharge (ESD) clamping transistor coupled to a ground terminal of a device. The apparatus further includes a switch coupled between a body terminal of the ESD clamping transistor and the around terminal.
Abstract translation: 在特定实施例中，一种装置包括耦合到装置的接地端子的静电放电（ESD）钳位晶体管。 该装置还包括耦合在ESD钳位晶体管的主体端子和周围端子之间的开关。
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公开(公告)号：US11430493B1
公开(公告)日：2022-08-30
申请号：US17204649
申请日：2021-03-17
Applicant: QUALCOMM Incorporated
Inventor： Seyed Arash Mirhaj , Ankit Srivastava , Sameer Wadhwa , Ren Li , Suren Mohan
IPC: G11C11/419 , G11C7/12 , G11C7/10 , G11C7/18
Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.
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公开(公告)号：US11372622B2
公开(公告)日：2022-06-28
申请号：US16811480
申请日：2020-03-06
Applicant: QUALCOMM Incorporated
Inventor： Ankit Srivastava
IPC: G06F7/57 , G11C11/41 , G11C11/412 , G11C11/419 , G06N20/00 , H03M1/38
Abstract: A compute-in-memory array is provided that includes a set of compute-in-memory bitcells that time share a shared capacitor connected between the set of compute-in-memory bitcells and a read bit line.
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Patent Agency Ranking
公开(公告)号：US11018687B1
公开(公告)日：2021-05-25
申请号：US15931337
申请日：2020-05-13
Applicant: QUALCOMM Incorporated
Inventor： Ankit Srivastava , Seyed Arash Mirhaj
Abstract: A time-multiplexed group of MAC circuits for a machine learning application is provided in which at least one MAC circuit in the time-multiplexed group also functions as a capacitive-digital-to-analog converter (CDAC) within a successive approximation analog-to-digital converter (ADC). A comparator in the ADC is shared by the time-multiplexed group of MAC circuits.
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公开(公告)号：US20150381161A1
公开(公告)日：2015-12-31
申请号：US14511800
申请日：2014-10-10
Applicant: QUALCOMM Incorporated
Inventor： Xinwang Zhang , Vijayakumar Dhanasekaran , Le Wang , Ankit Srivastava
CPC classification number: H03K17/161 , H03F1/26 , H03F2200/372 , H03K17/167 , H03K2217/0072
Abstract: A driver circuit includes detectors responsive to the operating region that a driven switch is operating in. The driver circuit is operative to drive the gate of the driven switch at a speed responsive to the output of the detectors.
Abstract translation: 驱动器电路包括响应于操作区域的检测器，驱动开关正在操作。驱动器电路用于以响应于检测器的输出的速度驱动从动开关的门。
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18.发明申请公开(公告)号：US20140254051A1
公开(公告)日：2014-09-11
申请号：US13794268
申请日：2013-03-11
Applicant: QUALCOMM INCORPORATED
Inventor： Ankit Srivastava , Matthew David Sienko , Eugene Robert Worley
CPC classification number: G05F1/10 , H01L27/0274 , H01L27/0277 , H01L27/0629 , H02H3/006 , H02H9/041 , H02H9/046
Abstract: A device includes a snapback clamp circuit configured to clamp a supply voltage in response to the supply voltage exceeding a trigger voltage level. In at least one embodiment, the snapback clamp circuit includes a clamp transistor and a programmable resistance portion that is responsive to a control signal to calibrate the trigger voltage level. Alternatively or in addition, the snapback clamp circuit may include a programmable bias device configured to calibrate the trigger voltage level by biasing a gate terminal of the clamp transistor. In another particular embodiment, a method of calibrating a snapback clamp circuit is disclosed. In another particular embodiment, a method of operating an integrated circuit is disclosed.
Abstract translation: 一种设备包括一个快速恢复钳位电路，配置成响应于超过触发电压电平的电源电压来钳位电源电压。 在至少一个实施例中，快速恢复钳位电路包括钳位晶体管和可编程电阻部分，其响应于控制信号来校准触发电压电平。 或者或另外，快速恢复钳位电路可以包括可编程偏置装置，其被配置为通过偏置钳位晶体管的栅极端子来校准触发电压电平。 在另一个具体实施例中，公开了一种校准快速恢复钳位电路的方法。 在另一个具体实施例中，公开了一种操作集成电路的方法。
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公开(公告)号：US20140098447A1
公开(公告)日：2014-04-10
申请号：US13645223
申请日：2012-10-04
Applicant: QUALCOMM INCORPORATED
Inventor： Ankit Srivastava , Eugene R Worley
IPC: H02H9/04
CPC classification number: H01L27/0285 , H02H9/046
Abstract: Electrostatic discharge protection for Class D power amplifiers is disclosed. In an exemplary embodiment, an apparatus includes an amplifier having an output transistor coupled to an interface pad, a snapback supply clamp coupled across first and second supplies of the amplifier and configured to provide a clamp voltage across the first and second supplies during ESD event; and a trigger circuit coupled to the output transistor, the trigger circuit configured to detect the clamp voltage and to enable the output transistor to provide a discharge path from the interface pad to the second supply when the clamp voltage is detected.
Abstract translation: 公开了D类功率放大器的静电放电保护。 在示例性实施例中，一种装置包括具有耦合到接口焊盘的输出晶体管的放大器，耦合在放大器的第一和第二电源上并被配置为在ESD事件期间在第一和第二电源上提供钳位电压的快速恢复电源钳位; 以及触发电路，其耦合到所述输出晶体管，所述触发电路被配置为检测所述钳位电压，并且使得所述输出晶体管能够在检测到所述钳位电压时提供从所述接口焊盘到所述第二电源的放电路径。
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公开(公告)号：US12135956B2
公开(公告)日：2024-11-05
申请号：US17197359
申请日：2021-03-10
Applicant: QUALCOMM Incorporated
Inventor： Seyed Arash Mirhaj , Ankit Srivastava , Sameer Wadhwa
Abstract: Various embodiments include devices and methods for a multi-bit multiplier-accumulator (MAC). Some embodiments may include an analog adder having a first adder capacitor. The first adder capacitor may add a plurality of single-bit MAC outputs by receiving the plurality of single-bit MAC outputs from a plurality of single-bit MACs, and storing the plurality of single-bit MAC outputs. In some embodiments, the analog adder may output a multi-bit MAC output based on addition of the stored plurality of single-bit MAC outputs.
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