公开(公告)号：US09383809B2

公开(公告)日：2016-07-05

申请号：US14079620

申请日：2013-11-13

Applicant: Qualcomm Incorporated

Inventor： Dexter Chun ,  Haw-Jing Lo

IPC: G06F1/00 ,  G06F1/32 ,  G11C7/10 ,  G11C11/4096 ,  G06F7/76

CPC classification number: G06F1/3275 ,  G06F1/32 ,  G06F1/3253 ,  G06F7/764 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4096

Abstract: Systems and methods are disclosed for reducing memory I/O power. One embodiment is a system comprising a system on chip (SoC), a DRAM memory device, and a data masking power reduction module. The SoC comprises a memory controller. The DRAM memory device is coupled to the memory controller via a plurality of DQ pins. The data masking power reduction module comprises logic configured to drive the DQ pins to a power saving state during a data masking operation.

Abstract translation: 公开了用于降低存储器I / O功率的系统和方法。 一个实施例是包括片上系统（SoC），DRAM存储器件和数据屏蔽功率降低模块的系统。 SoC包括一个内存控制器。 DRAM存储器件通过多个DQ引脚耦合到存储器控制器。 数据屏蔽功率降低模块包括被配置为在数据屏蔽操作期间将DQ引脚驱动到功率节省状态的逻辑。

公开(公告)号：US20200098420A1

公开(公告)日：2020-03-26

申请号：US16137496

申请日：2018-09-20

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Chun ,  Pratik Patel

IPC: G11C11/406 ,  G06F3/06

Abstract: Systems, methods, and computer programs are disclosed for refreshing a volatile memory. An embodiment of a method comprises storing, in a volatile memory device comprising a cell array having a plurality of rows with a correspond ng row address, a table specifying one of a data valid indicator and a data invalid indicator for each of the plurality of row addresses. The data valid indicator specifies that the corresponding row is in use, and the data invalid indicator specifies that the corresponding row is not in use. A memory controller initiates a refresh command. In response to the refresh command, the rows having the data valid indicator are refreshed while the rows having the data invalid indicator are skipped.

公开(公告)号：US10482943B2

公开(公告)日：2019-11-19

申请号：US15636565

申请日：2017-06-28

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Chun ,  Yanru Li

IPC: G11C7/00 ,  G11C11/406 ,  H01L27/108 ,  H03M13/09 ,  H03M13/11

Abstract: Systems and methods are disclosed for error correction control (ECC) for a refreshable memory device coupled to a system on a chip SoC. The memory device including a parity region and a user data region. A method includes determining with the SoC a first refresh rate for the user data region of the memory device and a second refresh rate for the parity region of the memory device, where the second refresh rate is different than the first refresh rate. Parity data is generated for a write operation of a user payload data (UPD) to the user data region of the memory device. The user data region of the memory device is refreshed at the first refresh rate and the parity region is refreshed at the second refresh rate.

公开(公告)号：US10310757B2

公开(公告)日：2019-06-04

申请号：US15684838

申请日：2017-08-23

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Larry Bassel ,  Thomas Zeng ,  Dexter Chun

IPC: G06F3/06

Abstract: Systems, methods, and computer programs are disclosed for reducing memory power consumption. An exemplary method comprises configuring a power saving memory balloon associated with a volatile memory. Memory allocations are steered to the power saving memory balloon. In response to initiating a memory power saving mode, data is migrated from the power saving memory balloon. A power saving feature is executed on the power saving memory balloon while in the memory power saving mode.

公开(公告)号：US09612648B2

公开(公告)日：2017-04-04

申请号：US13962746

申请日：2013-08-08

Applicant: Qualcomm Incorporated

Inventor： Dexter Chun ,  Yanru Li ,  Alex Tu ,  Haw-Jing Lo

IPC: G06F12/00 ,  G06F1/32 ,  G06F12/06 ,  G11C14/00

CPC classification number: G06F1/3275 ,  G06F12/0607 ,  G06F2212/1028 ,  G11C14/0009 ,  Y02D10/13 ,  Y02D10/14

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance.

公开(公告)号：US09430434B2

公开(公告)日：2016-08-30

申请号：US14033233

申请日：2013-09-20

Applicant: Qualcomm Incorporated

Inventor： Haw-Jing Lo ,  Dexter Chun

IPC: G06F13/16 ,  G06F13/40 ,  G06F1/32

CPC classification number: G06F13/4018 ,  G06F1/3253 ,  G06F1/3275 ,  G06F13/1678 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a DRAM memory system and a system on chip (SoC). The SoC is coupled to the DRAM memory system via a memory bus. The SoC comprises one or more memory controllers for processing memory requests from one or more memory clients for accessing the DRAM memory system. The one or more memory controllers are configured to selectively conserve memory power consumption by dynamically resizing a bus width of the memory bus.

Abstract translation: 公开了用于节省存储器系统中的功耗的系统和方法。 一种这样的系统包括DRAM存储器系统和片上系统（SoC）。 SoC通过存储器总线耦合到DRAM存储器系统。 SoC包括用于处理来自一个或多个存储器客户端的访问DRAM存储器系统的存储器请求的一个或多个存储器控制器。 一个或多个存储器控制器被配置为通过动态地调整存储器总线的总线宽度来选择性地节省存储器功耗。

公开(公告)号：US10579516B2

公开(公告)日：2020-03-03

申请号：US15457899

申请日：2017-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Chun ,  William Kimberly

IPC: G06F1/3287 ,  G06F12/02 ,  G06F13/40 ,  G06F13/16 ,  G06F1/3234 ,  G06F1/3221 ,  G06F1/3225 ,  G06F9/50

Abstract: Systems, methods, and computer programs are disclosed for providing power-efficient file system operation to a non-volatile block memory. An exemplary embodiment of a system comprises a non-volatile block memory having a file system, a dynamic random access memory (DRAM), and a system on chip (SoC). The SoC comprises a central processing unit (CPU), one or more non-core processors, a DRAM controller, a data interface coupled to an off-chip processor, and a multi-host storage controller. The CPU allocates a storage buffer in the non-volatile block memory. The multi-host storage controller comprises a virtualized client interface for providing the non-core and off-chip processors with direct read/write file system access using the allocated storage buffer while the CPU and the DRAM are in a low power state.

公开(公告)号：US10387333B2

公开(公告)日：2019-08-20

申请号：US15399625

申请日：2017-01-05

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Chun ,  Yanru Li

IPC: G06F21/79 ,  G06F12/14 ,  G06F21/60

Abstract: Systems and methods are disclosed for providing secure access to a non-volatile random access memory. One such method comprises sending an unlock password to a non-volatile random access memory (NVRAM) in response to a trusted boot program executing on a system on chip (SoC). The NVRAM compares the unlock password to a pass gate value provisioned in the NVRAM. If the unlock password matches the pass gate value, a pass gate is unlocked to enable the SoC to access a non-volatile cell array in the NVRAM.

公开(公告)号：US20190176838A1

公开(公告)日：2019-06-13

申请号：US15838777

申请日：2017-12-12

Applicant: QUALCOMM Incorporated

Inventor： Mohammad Reza KAKOEE ,  Rahul Gulati ,  Eric Mahurin ,  Suresh Kumar Venkumahanti ,  Dexter Chun

IPC: B60W50/02 ,  G06F11/10 ,  H03M13/05

Abstract: A system and a method for error-correction code (“ECC”) error handling is described herein. In one aspect, the system and method may operate an ECC function on raw data. The ECC function may include generating ECC syndrome data by an ECC syndrome data generating module. The ECC syndrome data may be derived from the raw data. The system and a method may further inject a fault based on the ECC syndrome data or the raw data. The system and a method may further determine whether the ECC error detected by the ECC checker corresponds to a malfunction of the ECC function or the fault injected based on the ECC syndrome data or the raw data.

公开(公告)号：US20190065087A1

公开(公告)日：2019-02-28

申请号：US15684838

申请日：2017-08-23

Applicant: QUALCOMM INCORPORATED

Inventor： YANRU LI ,  Larry Bassel ,  Thomas Zeng ,  Dexter Chun

IPC: G06F3/06

Abstract: Systems, methods, and computer programs are disclosed for reducing memory power consumption. An exemplary method comprises configuring a power saving memory balloon associated with a volatile memory. Memory allocations are steered to the power saving memory balloon. In response to initiating a memory power saving mode, data is migrated from the power saving memory balloon. A power saving feature is executed on the power saving memory balloon while in the memory power saving mode.