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    Register files for a digital signal processor operating in an interleaved multi-threaded environment
    11.
    发明授权
    Register files for a digital signal processor operating in an interleaved multi-threaded environment 有权
    为交错多线程环境中的数字信号处理器注册文件

    公开(公告)号：US09235418B2

    公开(公告)日：2016-01-12

    申请号：US14189313

    申请日：2014-02-25

    Applicant: QUALCOMM Incorporated

    Inventor： Muhammad Ahmed ,  Erich James Plondke ,  Lucian Codrescu ,  William C. Anderson

    IPC: G06F15/76 ,  G06F9/30 ,  G06F7/38 ,  G06F13/00 ,  G06F9/38

    CPC classification number: G06F9/30149 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/3885

    Abstract: A processor device includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution, The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register flies includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.

    Abstract translation: 处理器设备包括响应于存储器的存储器和定序器。 定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。 多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。 此外，多个寄存器苍蝇中的每一个包括多个数据读取端口，并且多个寄存器文件中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。

    DEDICATED ARITHMETIC ENCODING INSTRUCTION
    12.
    发明申请
    DEDICATED ARITHMETIC ENCODING INSTRUCTION 有权
    专用算术编码指令

    公开(公告)号：US20150349796A1

    公开(公告)日：2015-12-03

    申请号：US14288018

    申请日：2014-05-27

    Applicant: QUALCOMM Incorporated

    Inventor： Bo Zhou ,  Mao Zeng ,  Erich James Plondke ,  Lucian Codrescu ,  Shu Xiao ,  Junchen Du ,  Suhail Jalil

    IPC: H03M7/40

    CPC classification number: H03M7/4018 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/3895 ,  H04N19/13 ,  H04N19/42 ,  H04N19/91

    Abstract: A method includes executing, at a processor, a dedicated arithmetic encoding instruction. The dedicated arithmetic encoding instruction accepts a plurality of inputs including a first range, a first offset, and a first state and produces one or more outputs based on the plurality of inputs. The method also includes storing a second state, realigning the first range to produce a second range, and realigning the first offset to produce a second offset based on the one or more outputs of the dedicated arithmetic encoding instruction.

    Abstract translation: 一种方法包括在处理器处执行专用算术编码指令。 专用算术编码指令接受包括第一范围，第一偏移和第一状态的多个输入，并且基于多个输入产生一个或多个输出。 该方法还包括存储第二状态，重新对准第一范围以产生第二范围，以及基于专用算术编码指令的一个或多个输出来重新对准第一偏移以产生第二偏移。

    CONFIGURABLE TRANSLATION LOOKASIDE BUFFER
    13.
    发明申请
    CONFIGURABLE TRANSLATION LOOKASIDE BUFFER 审中-公开
    可配置翻译LOOKASIDE BUFFER

    公开(公告)号：US20140068225A1

    公开(公告)日：2014-03-06

    申请号：US14073190

    申请日：2013-11-06

    Applicant: QUALCOMM Incorporated

    Inventor： Erich James Plondke ,  Ajay Anant Ingle ,  Lucian Codrescu ,  Paul D. Bassett

    IPC: G06F12/10

    CPC classification number: G06F12/1027 ,  G06F2212/1028 ,  Y02D10/13

    Abstract: A particular method includes receiving at least one translation lookaside buffer (TLB) configuration indicator. The at least one TLB configuration indicator indicates a specific number of entries to be enabled at a TLB. The method further includes modifying a number of searchable entries of the TLB in response to the at least one TLB configuration indicator.

    Abstract translation: 一种特定的方法包括接收至少一个翻译后备缓冲器（TLB）配置指示符。 至少一个TLB配置指示符指示将在TLB处启用的特定数量的条目。 所述方法还包括响应于所述至少一个TLB配置指示符来修改所述TLB的可搜索条目的数量。

    Parity for instruction packets
    14.
    发明授权
    Parity for instruction packets 有权

    公开(公告)号：US10108487B2

    公开(公告)日：2018-10-23

    申请号：US15192981

    申请日：2016-06-24

    Applicant: QUALCOMM Incorporated

    Inventor： Erich James Plondke

    IPC: G06F11/10 ,  G06F9/30 ,  G06F12/0875

    Abstract: Systems and method of error checking for instructions method of error checking for instructions include an assembler for creating an instruction packet with one or more instructions, determining if a parity of the instruction packet matches a predesignated parity, and if the parity of the instruction packet does not match the predesignated parity, using a bit of the instruction packet to change parity of the instruction packet to match the predesignated parity. The instruction packet with the predesignated parity is stored in a memory, and may eventually be retrieved by a processor for execution. If there is an error in the instruction packet retrieved from the memory, the error is detected based on comparing the parity of the instruction packet to the predesignated parity.

    SYSTEMS AND METHODS OF EXECUTING MULTIPLE HYPERVISORS
    17.
    发明申请
    SYSTEMS AND METHODS OF EXECUTING MULTIPLE HYPERVISORS 有权
    多重执行机构的系统与方法

    公开(公告)号：US20140282508A1

    公开(公告)日：2014-09-18

    申请号：US13829023

    申请日：2013-03-14

    Applicant: QUALCOMM INCORPORATED

    Inventor： Erich James Plondke ,  Lucian Codrescu ,  Christopher Edward Koob ,  Piyush Patel ,  Thomas Andrew Sartorius

    IPC: G06F9/455

    CPC classification number: G06F9/45533 ,  G06F9/5016 ,  G06F12/109 ,  G06F2212/1021 ,  G06F2212/151 ,  G06F2212/656

    Abstract: An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.

    Abstract translation: 一种装置包括可在第一组处理器上执行的主管理程序，以及可在第二组处理器上执行的辅管理程序。 主管理程序可以定义资源的设置，次管理程序可以使用基于主管理程序定义的设置的资源。 例如，主管理程序可以为二级管理程序编程内存地址转换映射。 主管理程序和辅助管理程序可以包括它们自己的调度器。

    Systems and methods for cache line replacement
    19.
    发明授权
    Systems and methods for cache line replacement 有权
    用于缓存线替换的系统和方法

    公开(公告)号：US08812789B2

    公开(公告)日：2014-08-19

    申请号：US13894545

    申请日：2013-05-15

    Applicant: QUALCOMM Incorporated

    Inventor： Ajay Anant Ingle ,  Erich James Plondke ,  Lucian Codrescu

    IPC: G06F12/08

    CPC classification number: G06F12/0808 ,  G06F12/121 ,  G06F2212/1016 ,  Y02D10/13

    Abstract: A computer readable storage medium includes instructions that, when executed by a processor, cause the processor to receive an index value included in a cache invalidate by index instruction, an encoded way value, and an incrementer output value. The instructions further cause the processor to assign the index value as an identifier value in response to receiving the cache invalidate by index instruction. The identifier value indicates a cache line for replacement.

    Abstract translation: 计算机可读存储介质包括当由处理器执行时使处理器通过索引指令，编码方式值和递增器输出值来接收包括在高速缓存无效中的索引值的指令。 指令进一步导致处理器响应于通过索引指令接收到高速缓存无效而将索引值分配为标识符值。 标识符值表示用于替换的高速缓存行。

    REGISTER FILES FOR A DIGITAL SIGNAL PROCESSOR OPERATING IN AN INTERLEAVED MULTI-THREADED ENVIRONMENT
    20.
    发明申请
    REGISTER FILES FOR A DIGITAL SIGNAL PROCESSOR OPERATING IN AN INTERLEAVED MULTI-THREADED ENVIRONMENT 有权
    用于数字信号处理器的注册表文件在交互式多路径环境中运行

    公开(公告)号：US20140181468A1

    公开(公告)日：2014-06-26

    申请号：US14189313

    申请日：2014-02-25

    Applicant: QUALCOMM Incorporated

    Inventor： Muhammad Ahmed ,  Erich James Plondke ,  Lucian Codrescu ,  William C. Anderson

    IPC: G06F9/30

    CPC classification number: G06F9/30149 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/3885

    Abstract: A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.

    Abstract translation: 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。 处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。 多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。 此外，多个寄存器文件中的每一个包括多个数据读取端口，并且多个寄存器堆栈中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。

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