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公开(公告)号：US11606070B1
公开(公告)日：2023-03-14
申请号：US17470191
申请日：2021-09-09
Applicant: QUALCOMM Incorporated
Inventor： Mohamed Abouzied , Vinod Panikkath , Li Liu , Chuan Wang
Abstract: An aspect relates to an apparatus including a radio frequency (RF) signal power detector. The RF signal power detector includes a first current source configured to generate a first current based on a power level of a first RF signal; a transimpedance amplifier (TIA) configured to generate a first voltage based on the first current, wherein the TIA is coupled between a first upper voltage rail and a lower voltage rail; and a second current source configured to generate a second current related to the first current, wherein the first and second current sources are coupled in series between a second upper voltage rail and the lower voltage rail.
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公开(公告)号：US09379722B2
公开(公告)日：2016-06-28
申请号：US13926631
申请日：2013-06-25
Applicant: QUALCOMM Incorporated
Inventor： Wu-Hsin Chen , Sriramgopal Sridhara , Li Liu
CPC classification number: H03L7/18 , H03K3/017 , H03K5/1565 , H03K21/08
Abstract: A frequency divider with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit and at least one duty cycle adjustment circuit coupled in a feedback loop. The divider circuit(s) receive a clock signal at a first frequency and provide at least one divided signal at a second frequency, which is a fraction of the first frequency. The duty cycle adjustment circuit(s) adjust the duty cycle of the at least one divided signal and provide at least one duty cycle adjusted signal to the divider circuit(s). The divider circuit(s) may include first and second latches, and the duty cycle adjustment circuit(s) may include first and second duty cycle adjustment circuits. The first and second latches and the first and second duty cycle adjustment circuits may be coupled in a feedback loop and may perform divide-by-2.
Abstract translation: 公开了一种在反馈环路内进行占空比调节的分频器。 在示例性设计中，装置包括耦合在反馈回路中的至少一个除法器电路和至少一个占空比调整电路。 分频器电路以第一频率接收时钟信号，并以第二频率提供至少一个分频信号，该第二频率是第一频率的一部分。 占空比调整电路调整至少一个分频信号的占空比，并向分频器电路提供至少一个占空比调整信号。 分频器电路可以包括第一和第二锁存器，并且占空比调整电路可以包括第一和第二占空比调整电路。 第一和第二锁存器以及第一和第二占空比调整电路可以耦合在反馈回路中并且可以执行除以2。
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13.发明申请LOCAL OSCILLATOR (LO) GENERATOR WITH MULTI-PHASE DIVIDER AND PHASE LOCKED LOOP 有权具有多相分离器和相位锁定环路的本地振荡器（LO）发生器公开(公告)号：US20140273904A1
公开(公告)日：2014-09-18
申请号：US13828879
申请日：2013-03-14
Applicant: QUALCOMM INCORPORATED
Inventor： Li Liu , Chiewcharn Narathong
IPC: H04B1/16
Abstract: Techniques for generating a local oscillator (LO) signal are disclosed. In one design, an apparatus includes an oscillator, a divider, and a phase locked loop (PLL). The oscillator receives a control signal and provides an oscillator signal having a frequency determined by the control signal. The divider receives the oscillator signal and generates multiple divided signals of different phases. The PLL receives a reference signal and a selected divided signal and generates the control signal for the oscillator. The divider is powered on and off periodically and wakes up in one of multiple possible states, with each state being associated with a different phase of the selected divided signal. Phase continuity of the selected divided signal is ensured by using the divider in a feedback loop with the PLL. The PLL locks the selected divided signal to the reference signal, and the selected divided signal has continuous phase due to the reference signal having continuous phase.
Abstract translation: 公开了用于产生本地振荡器（LO）信号的技术。 在一种设计中，装置包括振荡器，分频器和锁相环（PLL）。 振荡器接收控制信号并提供具有由控制信号确定的频率的振荡器信号。 分频器接收振荡器信号并产生不同相位的多个分频信号。 PLL接收参考信号和选择的分频信号，并产生振荡器的控制信号。 分频器周期性地通电和关断，并在多个可能状态之一中唤醒，每个状态与所选分频信号的不同相位相关联。 通过在与PLL的反馈环路中使用分频器来确保选择的分频信号的相位连续性。 PLL将所选择的分频信号锁定到参考信号，并且由于具有连续相位的参考信号，所选择的分频信号具有连续相位。
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公开(公告)号：US20140070899A1
公开(公告)日：2014-03-13
申请号：US13755130
申请日：2013-01-31
Applicant: QUALCOMM INCORPORATED
Inventor： Li Liu , Chiewcharn Narathong
CPC classification number: H03B5/1228 , H01L25/00 , H01L2924/0002 , H03B5/04 , H03B5/1209 , H03B5/1243 , H03B2200/0088 , H03L1/00 , H03L7/099 , H01L2924/00
Abstract: A voltage controlled oscillator (VCO) core for cancelling a supply noise is described. The VCO core includes an input node that receives the supply noise. The VCO core also includes a noise path coupled to the input node. The VCO core additionally includes a cancellation path coupled to the input node and the noise path. The cancellation path includes a programmable gain circuit coupled with a first terminal of a varactor. The supply noise passes through the programmable gain circuit to produce a cancellation noise.
Abstract translation: 描述了用于消除电源噪声的压控振荡器（VCO）芯。 VCO核心包括接收电源噪声的输入节点。 VCO核心还包括耦合到输入节点的噪声路径。 VCO核心还包括耦合到输入节点和噪声路径的消除路径。 消除路径包括与变容二极管的第一端子耦合的可编程增益电路。 电源噪声通过可编程增益电路产生消除噪声。
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公开(公告)号：US12255586B2
公开(公告)日：2025-03-18
申请号：US18060295
申请日：2022-11-30
Applicant: Qualcomm Incorporated
Inventor： Mohamed Abouzied , Chuan Wang , Anosh Davierwalla , Muhammad Hassan , Vinod Panikkath , Li Liu
Abstract: An apparatus is disclosed for oscillator feedthrough calibration, such as a component arrangement that can be calibrated to account for signal leakage from an oscillator coupled to a mixer circuit. In example aspects, the apparatus includes a mixer circuit having a first stage, a second stage, and tuning circuitry. The first stage includes at least one transistor coupled between a mixer input and a mixer output. The second stage includes one or more transistors coupled between the at least one transistor of the first stage and the mixer output. The one or more transistors are also coupled between a local oscillator signal input and the mixer output. The tuning circuitry includes at least one current source coupled to the at least one transistor of the first stage.
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Patent Agency Ranking
公开(公告)号：US11942971B2
公开(公告)日：2024-03-26
申请号：US17686794
申请日：2022-03-04
Applicant: QUALCOMM Incorporated
Inventor： Chuan Wang , Li Liu , Wu-Hsin Chen , Vinod Panikkath , Yunfei Feng , Muhammad Hassan
CPC classification number: H04B1/0057 , H04B1/0035 , H04B1/0483 , H04B2001/0408
Abstract: Aspects described herein include devices and methods with chain routing of signals for massive antenna arrays. In some aspects, an apparatus is provided that includes a first millimeter wave (mmW) transceiver having a first port, a second port, one or more antenna elements, a plurality of chain mmW transceiver ports, and switching circuitry. The switching circuitry is controllable by control data to route portions of a merged clock and data signal and a merged control and data signal between a first route between the one or more antenna elements and the first port and a second route between the one or more antenna elements and the second port and a third route between the first port and the plurality of chain mmW transceiver ports and a fourth route between the second port and the plurality of chain mmW transceiver ports.
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公开(公告)号：US11271328B2
公开(公告)日：2022-03-08
申请号：US16140127
申请日：2018-09-24
Applicant: Qualcomm Incorporated
Inventor： Li Liu , Kevin Hsi Huai Wang , Yunfei Feng , Chuan Wang , Gurkanwal Sahota
Abstract: An apparatus is disclosed for a hybrid wireless transceiver architecture that supports multiple antenna arrays. In an example aspect, the apparatus includes a first antenna array, a second antenna array, and a wireless transceiver. The wireless transceiver includes first dedicated circuitry dedicated to the first antenna array and second dedicated circuitry dedicated to the second antenna array. The wireless transceiver also includes shared circuitry that is shared with both the first antenna array and the second antenna array.
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18.发明授权公开(公告)号：US09344270B2
公开(公告)日：2016-05-17
申请号：US13829232
申请日：2013-03-14
Applicant: QUALCOMM Incorporated
Inventor： Li Liu , Praveen-Kumar Sampath , Lai Kan Leung , Chiewcharn Narathong , Soon-Seng Lau , Ketan Humnabadkar , Raghu Narayan Challa , Devavrata Vasant Godbole
CPC classification number: H04L7/0331 , H03B21/01 , H03D3/009 , H04W52/02 , H04W52/0209 , Y02D70/1222 , Y02D70/1262 , Y02D70/142 , Y02D70/144 , Y02D70/164
Abstract: Techniques for detecting and correcting phase discontinuity of a local oscillator (LO) signal are disclosed. In one design, a wireless device includes an LO generator and a phase detector. The LO generator generates an LO signal used for frequency conversion and is periodically powered on and off. The phase detector detects the phase of the LO signal when the LO generator is powered on. The detected phase of the LO signal is used to identify phase discontinuity of the LO signal. The wireless device may further include (i) a single-tone generator that generates a single-tone signal used to detect the phase of the LO signal, (ii) a downconverter that downconverts the single-tone signal with the LO signal and provides a downconverted signal used by the phase detector to detect the phase of LO signal, and (iii) phase corrector that corrects phase discontinuity of the LO signal in the analog domain or digital domain.
Abstract translation: 公开了用于检测和校正本地振荡器（LO）信号的相位不连续性的技术。 在一种设计中，无线设备包括LO发生器和相位检测器。 LO发生器产生用于频率转换的LO信号，并且周期性地通电和关断。 当LO发生器通电时，相位检测器检测LO信号的相位。 LO信号的检测相位用于识别LO信号的相位不连续性。 无线设备还可以包括（i）生成用于检测LO信号的相位的单音信号的单音发生器，（ii）下变频器，其使用LO信号对单音信号进行下变频，并提供 相位检测器用于检测LO信号的相位的下变频信号，以及（iii）校正模拟域或数字域中的LO信号的相位不连续性的相位校正器。
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19.发明授权Pseudo-CML latch and divider having reduced charge sharing between output nodes 有权伪CML锁存器和分压器具有降低的输出节点之间的电荷共享公开(公告)号：US09059686B2
公开(公告)日：2015-06-16
申请号：US13926680
申请日：2013-06-25
Applicant: QUALCOMM Incorporated
Inventor： Wu-Hsin Chen , Li Liu , Jianyun Hu
CPC classification number: H03K3/017 , H01L21/823871 , H03K3/356121 , H03K3/356139
Abstract: In one example, a high-speed divider includes two identical pseudo-CML latches and four output inverters. Each latch includes a pair of cross-coupled signal holding transistors. A first P-channel pull-up circuit pulls up on a second output node QB of the latch. A second P-channel pull-up circuit pulls up on a first output node Q of the latch. A pull-down circuit involves four N-channel transistors. This pull-down circuit: 1) couples the QB node to ground when a clock signal CK is high and a data signal D is high, 2) couples the Q node to ground when CK is high and D is low, 3) prevents a transfer of charge between the QB and Q nodes through the pull-down circuit when D transitions during a time period when CK is low, and 4) decouples the QB and Q nodes from the pull-down circuit when CK is low.
Abstract translation: 在一个示例中，高速分频器包括两个相同的伪CML锁存器和四个输出反相器。 每个锁存器包括一对交叉耦合的信号保持晶体管。 第一P沟道上拉电路在锁存器的第二输出节点QB上拉起。 第二P沟道上拉电路在锁存器的第一输出节点Q上拉起。 下拉电路包括四个N沟道晶体管。 该下拉电路：1）当时钟信号CK为高电平且数据信号D为高电平时，将QB节点耦合到地，2）当CK为高电平且D为低电平时将Q节点接地，3）防止 当CK为低电平时，D转换时，通过下拉电路在QB和Q节点之间传输电荷;以及4）当CK为低电平时，将QB和Q节点与下拉电路解耦。
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公开(公告)号：US20140266479A1
公开(公告)日：2014-09-18
申请号：US13836932
申请日：2013-03-15
Applicant: QUALCOMM INCORPORATED
Inventor： Sujiang Rong , Li Liu , Yiwu Tang
CPC classification number: H03B5/1228 , H03B5/02 , H03B5/1215 , H03B5/1296 , H03B2200/0082 , H03B2200/009
Abstract: A method, an apparatus, and a computer program product are provided. The apparatus provides a VCO signal. The apparatus is a VCO. The apparatus includes a first transconductance circuit. The apparatus further includes a second transconductance circuit coupled with the first transconductance circuit. The second transconductance circuit has a first configuration/mode (e.g., CMOS configuration/mode) and a second configuration/mode (e.g., NMOS configuration/mode or PMOS configuration/mode). The second transconductance circuit is configured to couple an input of the second transconductance circuit to the first transconductance circuit in the first configuration/mode. The second transconductance circuit is configured to isolate the input of the second transconductance circuit from the first transconductance circuit in the second configuration/mode. The second transconductance circuit may include a first transistor and a second transistor, and the input may be a gate of each of the first transistor and the second transistor.
Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置提供VCO信号。 该装置是VCO。 该装置包括第一跨导电路。 该装置还包括与第一跨导电路耦合的第二跨导电路。 第二跨导电路具有第一配置/模式（例如，CMOS配置/模式）和第二配置/模式（例如，NMOS配置/模式或PMOS配置/模式）。 第二跨导电路被配置为在第一配置/模式中将第二跨导电路的输入耦合到第一跨导电路。 第二跨导电路被配置为在第二配置/模式中将第二跨导电路的输入与第一跨导电路隔离。 第二跨导电路可以包括第一晶体管和第二晶体管，并且输入可以是第一晶体管和第二晶体管中的每一个的栅极。
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